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marcan42's profile
Hector Martin
Hector Martin
Hector Martin
@marcan42

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Hector Martin

@marcan42

If it ain't broke, I'll fix it! I'm porting Linux to Apple Silicon Macs at @AsahiLinux. http://patreon.com/marcan  | http://github.com/sponsors/marcan 

Tokyo, Japan
marcan.st
Joined May 2009

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    1. Hector Martin‏ @marcan42 22 Dec 2020
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      If there's a lesson I learned with Glasgow, it's that transparent bidirectional level shifters of any kind are evil. revA/B are broken for that reason (e.g. the I²C applet will never work), and revC0 pull-up support was broken because we used I²C-specific ones internally. 🤮

      2 replies 1 retweet 56 likes
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    2. Hector Martin‏ @marcan42 22 Dec 2020
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      "Why is my I²C bus self-oscillating at 3MHz‽" (oh yeah and it's unrecoverable) Second lesson was that voltage regulators are 1-bit DRAM chips with ~1-2 minute data retention when powered off.

      3 replies 1 retweet 42 likes
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    3. Andrew Zonenberg‏ @azonenberg 23 Dec 2020
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      Replying to @marcan42

      That was why I designed such a complex I/O cell for CLARKE (formerly STARSHIPRAIDER). I actually used two different unidirectional output buffers depending on VCCIO, and a comparator for the input. More expensive, but far more flexible than one magic chip.

      1 reply 0 retweets 4 likes
    4. Andrew Zonenberg‏ @azonenberg 23 Dec 2020
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      Replying to @azonenberg @marcan42

      I put the project on ice ~2 years ago because of my house renovation and not having a fast enough scope to adequately debug it. Maybe I can get back to it soonish.

      1 reply 0 retweets 3 likes
      Hector Martin‏ @marcan42 23 Dec 2020
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      Replying to @azonenberg

      Well, you went full crazy spec for yours :-) Glasgow is happy with bidirectional shifters *with direction input*. The reason revA/B didn't use those was to save FPGA pins to avoid having to use a BGA chip...

      12:24 AM - 23 Dec 2020
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      • Tom Keddie meowy catgirl
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        1. Hector Martin‏ @marcan42 23 Dec 2020
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          Replying to @marcan42 @azonenberg

          OTOH, since revE will be modular, we can have *all of* dumb unidirectional or slow-config-directional "gimme twice the I/Os" modules, revC style bidir I/O modules at 2 FPGA pins per I/O, and crazy CLARKE style do it all frontends :)

          1 reply 0 retweets 2 likes
        2. Andrew Zonenberg‏ @azonenberg 23 Dec 2020
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          Replying to @marcan42

          Yeah the CLARKE frontend design is 4 pins per channel: LVCMOS33 output + enable, then LVDS input. Each 8-bit IO card also gets I2C control and power. It will eventually synthesize VCCIO on board but I never got that far.

          1 reply 0 retweets 1 like
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