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What does the team plan on adding in the future revs?
revD is revC minus the LVDS header but with 32 I/Os. revE is a total redesign based on ECP5 with high-speed IO, Ethernet, and a modular architecture, but maintaining source-level applet compatibility. That's the plan anyway.
Oh I need those 32 I/O (I have procrastinated on debugging my Z80 based Nascom ). Glasgow marks the first time I actually get to use the fabled “adapt on the fly” promise of FPGA and it wouldn’t have been possible with IceStorm/Yosys/NextPNR ... Thanks y’all!
WithOUT, but you got that
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