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marcan42's profile
Hector Martin
Hector Martin
Hector Martin
@marcan42

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Hector Martin

@marcan42

If it ain't broke, I'll fix it! I'm porting Linux to Apple Silicon Macs at @AsahiLinux. http://patreon.com/marcan  | http://github.com/sponsors/marcan 

Tokyo, Japan
marcan.st
Joined May 2009

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    1. Hector Martin‏ @marcan42 19 Dec 2020
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      And by the way, for the repairability folks: replaceable RAM on mobile devices is going away for good reason. Two SODIMMs is 128 bits of multi-GHz bus across multiple cm of board and a connector. That *eats* power. This isn't manufacturers being out to screw us, it's physics.

      13 replies 35 retweets 222 likes
      Show this thread
    2. ash‏ @mutesplash 19 Dec 2020
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      Replying to @marcan42

      Put them in a socket? 🤷‍♂️

      1 reply 0 retweets 1 like
    3. Hector Martin‏ @marcan42 19 Dec 2020
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      Replying to @mutesplash

      What *kind* of socket? Even if you do a CPU socket thing ($$$ and adds thickness) just making space for the thing plus the interconnect significantly increases total trace length. There's a reason why the M1 has ~0mm between the SoC die and the memory dies.

      3 replies 0 retweets 26 likes
    4. Paolo G. Giarrusso‏ @Blaisorblade 19 Dec 2020
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      Replying to @marcan42 @mutesplash

      Makes sense, but how bad will 32GB RAM or more be? That must increase distance from the CPU, so how bad does performance per watt degrade?

      1 reply 0 retweets 1 like
    5. Hector Martin‏ @marcan42 19 Dec 2020
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      Replying to @Blaisorblade @mutesplash

      We can stack lots of memory dies together these days. We'll see what Apple does there.

      1 reply 0 retweets 1 like
      Hector Martin‏ @marcan42 19 Dec 2020
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      Replying to @marcan42 @Blaisorblade @mutesplash

      But the immediately obvious answer here is that the M1 has two memory chips off to one side, and there's a whole other 3 sides they could put memory chips on :-)

      6:56 PM - 19 Dec 2020
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      • woofoo Paolo G. Giarrusso
      1 reply 0 retweets 2 likes
        1. New conversation
        2. Dr. Thorn‏ @iamtommythorn 19 Dec 2020
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          Replying to @marcan42 @Blaisorblade @mutesplash

          The floor plan has to be ready for that. The physical distance is not trivial so I doubt they would do that. You want the cache in between memory controller and the core, ideally.

          1 reply 0 retweets 1 like
        3. Hector Martin‏ @marcan42 19 Dec 2020
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          Replying to @iamtommythorn @Blaisorblade @mutesplash

          I'm thinking their next silicon, not the M1. I don't think they will be releasing 32G hardware with the M1.

          0 replies 0 retweets 3 likes
        4. End of conversation

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