Hector Martin

See the next tweet. Apple made the M1 able to switch to x86's consistency model. No other ARM chip can do that.

Hmmm... no. NVIDIA Denver and Carmel processors (64-bit Tegra K1 and Tegra Xavier) implement sequential consistency as the memory model *for everything*, which is even stronger than x86's. So "no other ARM chip" doesn't apply, and there are others too in server land...

Also Arm Cortex cores have much faster barriers than before, took them a while though. (and Qualcomm's SD820 Kryo cores had very fast barriers, but RIP) Please don't use arguments like that, it just hurts credibility on what you write more than anything...

Okay, I didn't know about Denver and Carmel having that property... but those also aren't ARM chips, they're a proprietary nVidia architecture running "rOsetta" and pretending to be ARM, so it's no surprise they're special :-)

Fast barriers don't help unless they're practically *free*; you can't really predict what loads/stores of x86 code need to have the properties of the x86 model, so you pretty much have to do it for all of them.

Yeah, that's being handled through multiple ways, one of which having chips where uncontended atomics are as cheap as a regular memory access. Change to use ARMv8.1-A atomics in the JIT-generated code because of those reasons was rolled out in Windows 10 since a bit.

Generally, Arm server cores (not from Arm themselves, which keep the weak memory model, opting for the optimize barriers and atomics path only) use the TSO memory model. Apple chose switchable memory model... and NVIDIA chose SC.

It's quite intriguing though to see such core aspects of the architecture vary across implementers, because Arm only imposes a baseline, not "your core has to implement a weak memory model" in their rules.