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marcan42's profile
Hector Martin
Hector Martin
Hector Martin
@marcan42

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Hector Martin

@marcan42

If it ain't broke, I'll fix it! I'm porting Linux to Apple Silicon Macs at @AsahiLinux. http://patreon.com/marcan  | http://github.com/sponsors/marcan 

Tokyo, Japan
marcan.st
Joined May 2009

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    1. Hector Martin‏ @marcan42 17 Nov 2020
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      As for Rosetta 2, it's good, but I'm still *really* curious how it'll do in the audio domain. We're talking lots of floating point processing with some integer mixed in, written by lots of different teams, some scalar, some vector, *definitely* a lot of it not well optimized.

      2 replies 0 retweets 41 likes
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    2. Hector Martin‏ @marcan42 17 Nov 2020
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      And with hard realtime constraints - if the JIT fires off anything substantial in the audio processing thread, you *will* get a dropout - and even if it's not substantial, you'll probably get a pile of priority inversion hazards that will cause inconsistent dropouts.

      3 replies 0 retweets 29 likes
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    3. Hector Martin‏ @marcan42 17 Nov 2020
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      So it looks like for day-to-day stuff Mac users can probably be confident that they won't lose much vs. their older Intel Mac under Rosetta 2, and gain in many instances. But I wouldn't put my money on M1+R2 for all workloads yet.

      1 reply 0 retweets 23 likes
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    4. Hector Martin‏ @marcan42 17 Nov 2020
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      It'll be interesting to see these performance details worked out in more detail; e.g. people have talked about M1 being way faster at ObjC object management, so presumably it has *way* faster atomics. That matters a lot for some kinds of software, and not at all for others.

      2 replies 0 retweets 30 likes
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    5. Hector Martin‏ @marcan42 17 Nov 2020
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      But the question is how, and why - presumably their bus system is tighter than typical x86 ones? I'm looking forward to a deeper dive, and whether AMD/Intel care to improve this in the future.

      1 reply 1 retweet 25 likes
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    6. Hector Martin‏ @marcan42 17 Nov 2020
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      Also, remember that Apple cheated with their control over the CPU for Rosetta 2. Getting R2 x86 performance on any other ARM is impossible, due to the memory model mismatch. You have to massively slow down all loads and stores.

      3 replies 5 retweets 51 likes
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    7. Hector Martin‏ @marcan42 17 Nov 2020
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      So Apple straight up implemented the x86 consistency model on their cores. That's the kind of high-impact detail that makes or breaks emulation performance for a different arch. Did they do this for any other x86-isms? Nobody knows so far.

      8 replies 31 retweets 139 likes
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    8. Erin  ✨ 💽‏ @erincandescent 18 Nov 2020
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      Replying to @marcan42 @whitequark

      n.b. the x86 consistency model is a part of the architecture since... one of the 8.3 extensions, that's implemented in A55/75 and newer. Of course, only with specific instructions, but they're not inherently slower except that you lose addressing mode flexibility

      1 reply 2 retweets 22 likes
    9. Erin  ✨ 💽‏ @erincandescent 18 Nov 2020
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      Replying to @erincandescent @marcan42 @whitequark

      I feel like this detail is... probably less of a dramatic impact than people think. It's not like you're spilling really expensive memory barriers everywhere without it or anything

      1 reply 0 retweets 7 likes
    10. Erin  ✨ 💽‏ @erincandescent 18 Nov 2020
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      Replying to @erincandescent @marcan42 @whitequark

      (Its also worthwhile considering that its' not like everyone else is ignoring x86 emulation performance - there are a bunch of instructions which no documentation will tell you exist to remove x86 emulation pain points, but that's very much why they're there. e.g. carry invert!)

      1 reply 0 retweets 14 likes
      Hector Martin‏ @marcan42 18 Nov 2020
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      Replying to @erincandescent @whitequark

      What, are you saying "Javascript" in instruction names is kosher, but "x86" isn't? :-) Good to hear this is being taken into account too. Do you have a reference for the new instructions? I'm having trouble finding it.

      8:45 AM - 18 Nov 2020
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      • hell writes memory initialization code for fun Tyson Key Erin ✨💽 Jessica 🌙
      2 replies 0 retweets 4 likes
        1. Ridley @ a safe distance‏ @11rcombs 18 Nov 2020
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          Replying to @marcan42 @erincandescent @whitequark

          tfw no DecodeUpToFifteenBytesOfPrefixes instruction

          0 replies 0 retweets 5 likes
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        2. Erin  ✨ 💽‏ @erincandescent 18 Nov 2020
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          Replying to @marcan42 @whitequark

          CFINV https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/cfinv-invert-carry-flag … & rest of the Flag Manipulation Extension is to help with Subtract-with-(carry/borrow)/PUSHF/POPF (LDAP|STL)U?R[BH]? implement the x86 memory model (i.e if you use those for all loads/stores you're consistent with x86)

          1 reply 2 retweets 12 likes
        3. Erin  ✨ 💽‏ @erincandescent 18 Nov 2020
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          Replying to @erincandescent @marcan42 @whitequark

          Note: Specifically LDAPR, not LDAR; LDAPR has weaker semantics than LDAR (LDAPR is an acquirer barrier against store releases with that specific address, LDAR is a general acquire barrier)

          0 replies 0 retweets 4 likes
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