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marcan42's profile
Hector Martin
Hector Martin
Hector Martin
@marcan42

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Hector Martin

@marcan42

If it ain't broke, I'll fix it! I'm porting Linux to Apple Silicon Macs at @AsahiLinux. http://patreon.com/marcan  | http://github.com/sponsors/marcan 

Tokyo, Japan
marcan.st
Joined May 2009

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    1. Hector Martin‏ @marcan42 17 Nov 2020
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      That said, it is somewhat reasonable to assume that M1 is likely to trend ahead as stuff is better optimized for ARM. But we don't know what kind of gains are yet to be had; some things might have reached peak already. So things will get interesting from here on.

      2 replies 2 retweets 33 likes
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    2. Hector Martin‏ @marcan42 17 Nov 2020
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      Once we have more real-world app tests to use as comparisons, we'll have a better idea of how the *practical* performance of the M1 compares with the current x86 crop.

      1 reply 0 retweets 21 likes
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    3. Hector Martin‏ @marcan42 17 Nov 2020
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      All this said, it looks like Apple has gone all-in on the "desktop experience". The really strong single-core perf (I wonder how much of that can be attributed to "x86 legacy garbage still has a cost"?), the awesome SSD, GPU, etc.

      1 reply 0 retweets 37 likes
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    4. Hector Martin‏ @marcan42 17 Nov 2020
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      It's no wonder the M1 Macs are beating the pants off of the previous Intel offering there. But Intel has been *sucking badly* for years, and there are a pile of improvements other than the CPU.

      1 reply 0 retweets 34 likes
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    5. Hector Martin‏ @marcan42 17 Nov 2020
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      As for Rosetta 2, it's good, but I'm still *really* curious how it'll do in the audio domain. We're talking lots of floating point processing with some integer mixed in, written by lots of different teams, some scalar, some vector, *definitely* a lot of it not well optimized.

      2 replies 0 retweets 41 likes
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    6. Hector Martin‏ @marcan42 17 Nov 2020
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      And with hard realtime constraints - if the JIT fires off anything substantial in the audio processing thread, you *will* get a dropout - and even if it's not substantial, you'll probably get a pile of priority inversion hazards that will cause inconsistent dropouts.

      3 replies 0 retweets 29 likes
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    7. Hector Martin‏ @marcan42 17 Nov 2020
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      So it looks like for day-to-day stuff Mac users can probably be confident that they won't lose much vs. their older Intel Mac under Rosetta 2, and gain in many instances. But I wouldn't put my money on M1+R2 for all workloads yet.

      1 reply 0 retweets 23 likes
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    8. Hector Martin‏ @marcan42 17 Nov 2020
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      It'll be interesting to see these performance details worked out in more detail; e.g. people have talked about M1 being way faster at ObjC object management, so presumably it has *way* faster atomics. That matters a lot for some kinds of software, and not at all for others.

      2 replies 0 retweets 30 likes
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    9. Hector Martin‏ @marcan42 17 Nov 2020
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      But the question is how, and why - presumably their bus system is tighter than typical x86 ones? I'm looking forward to a deeper dive, and whether AMD/Intel care to improve this in the future.

      1 reply 1 retweet 25 likes
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    10. Hector Martin‏ @marcan42 17 Nov 2020
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      Also, remember that Apple cheated with their control over the CPU for Rosetta 2. Getting R2 x86 performance on any other ARM is impossible, due to the memory model mismatch. You have to massively slow down all loads and stores.

      3 replies 5 retweets 51 likes
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      Hector Martin‏ @marcan42 17 Nov 2020
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      So Apple straight up implemented the x86 consistency model on their cores. That's the kind of high-impact detail that makes or breaks emulation performance for a different arch. Did they do this for any other x86-isms? Nobody knows so far.

      9:59 PM - 17 Nov 2020
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      • Parker Reed Jānis Circenis R. Gaab 🇪🇺 Тибснорг Пеккимоози hell writes memory initialization code for fun Tyson Key Jasper Bakker UCX Sagar Wadhwa eli b.
      8 replies 31 retweets 139 likes
        1. New conversation
        2. ᴊᴀᴍᴇꜱ ᴊᴜꜱᴛ ᴊᴀᴍᴇꜱ‏ @purpleidea 17 Nov 2020
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          Replying to @marcan42

          Is there some more information about this specifically or something I could read (wikipedia or similar) to get a rough idea of what they had to do to make this x86 consistency model work with their M1 chip? (I'm a nerd, but not genius at hardware specific stuff like you.)

          2 replies 0 retweets 4 likes
        3. Mike‏ @cmsimike 17 Nov 2020
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          Replying to @purpleidea @marcan42

          Same - any info about that would be appreciated. I also wonder if this implementation detail they can toss once they’re done with x86 emulation or if this is a benefit to running aarch64

          0 replies 0 retweets 0 likes
        4. End of conversation
        1. New conversation
        2. Matt  🔞‏ @coburn64 17 Nov 2020
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          Replying to @marcan42

          Amazing read mate. I am curious to see how the Apple chips perform against AMD. (yeah, let’s just say Intel has fallen down the mountain...) Although one thing that makes me wonder... how will games run under Rosetta 2?

          1 reply 0 retweets 0 likes
        3. Antoine‏ @ntnmrndn 18 Nov 2020
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          Replying to @coburn64

          They played the latest tumb raider back in the wwdc (so ... probably before the M1) on emulated x86. Looked great.

          0 replies 0 retweets 0 likes
        4. End of conversation
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        2. Bo Tian‏ @botian_ 17 Nov 2020
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          Replying to @marcan42

          what's stopping Qualcomm or Samsung from doing the same?

          1 reply 0 retweets 2 likes
        3. Hector Martin‏ @marcan42 17 Nov 2020
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          Replying to @botian_

          Nothing, if they care about this. You need an ARM architectural license and custom cores, though. I'm not sure if Qualcomm could retrofit it into their "semi-custom" Cortex variants. Samsung is mixing vanilla Cortex stuff with Exynos, they could only do it for the latter.

          1 reply 0 retweets 3 likes
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        2. Erin  ✨ 💽‏ @erincandescent 18 Nov 2020
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          Replying to @marcan42 @whitequark

          n.b. the x86 consistency model is a part of the architecture since... one of the 8.3 extensions, that's implemented in A55/75 and newer. Of course, only with specific instructions, but they're not inherently slower except that you lose addressing mode flexibility

          1 reply 2 retweets 22 likes
        3. Erin  ✨ 💽‏ @erincandescent 18 Nov 2020
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          Replying to @erincandescent @marcan42 @whitequark

          I feel like this detail is... probably less of a dramatic impact than people think. It's not like you're spilling really expensive memory barriers everywhere without it or anything

          1 reply 0 retweets 7 likes
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        2. kbob‏ @kernlbob 18 Nov 2020
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          Replying to @marcan42

          This reminds me of the PowerPC 601e circa 1994. The original 601 did not have enough I cache to hold the MC68K emulator, so Appled asked IBM for a new chip with bigger I cache.

          1 reply 0 retweets 3 likes
        3. Dantooine's Inferno ♥︎ Black Lives Matter‏ @Symbo1ics 30 Nov 2020
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          Replying to @kernlbob @marcan42

          (There were also 2 major versions of the emulator, the first interpreted i think, and the much improved one was JIT.)

          0 replies 0 retweets 1 like
        4. End of conversation

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