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All this said, it looks like Apple has gone all-in on the "desktop experience". The really strong single-core perf (I wonder how much of that can be attributed to "x86 legacy garbage still has a cost"?), the awesome SSD, GPU, etc.
It's no wonder the M1 Macs are beating the pants off of the previous Intel offering there. But Intel has been *sucking badly* for years, and there are a pile of improvements other than the CPU.
As for Rosetta 2, it's good, but I'm still *really* curious how it'll do in the audio domain. We're talking lots of floating point processing with some integer mixed in, written by lots of different teams, some scalar, some vector, *definitely* a lot of it not well optimized.
And with hard realtime constraints - if the JIT fires off anything substantial in the audio processing thread, you *will* get a dropout - and even if it's not substantial, you'll probably get a pile of priority inversion hazards that will cause inconsistent dropouts.
So it looks like for day-to-day stuff Mac users can probably be confident that they won't lose much vs. their older Intel Mac under Rosetta 2, and gain in many instances. But I wouldn't put my money on M1+R2 for all workloads yet.
It'll be interesting to see these performance details worked out in more detail; e.g. people have talked about M1 being way faster at ObjC object management, so presumably it has *way* faster atomics. That matters a lot for some kinds of software, and not at all for others.
But the question is how, and why - presumably their bus system is tighter than typical x86 ones? I'm looking forward to a deeper dive, and whether AMD/Intel care to improve this in the future.
Also, remember that Apple cheated with their control over the CPU for Rosetta 2. Getting R2 x86 performance on any other ARM is impossible, due to the memory model mismatch. You have to massively slow down all loads and stores.
So Apple straight up implemented the x86 consistency model on their cores. That's the kind of high-impact detail that makes or breaks emulation performance for a different arch. Did they do this for any other x86-isms? Nobody knows so far.
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