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Speculation is OK! There just has to be a way to reset *all* microarchitectural state before starting a test run, so speculation happens the same way every time. For DDR, you’d have to define a worst-case # of cycles for an access, then artificially delay all accesses to that.https://twitter.com/rzidane360/status/1280737724916355072 …
This doesn't work. The problem is the worst case timings are *horrendous* and you would completely destroy performance if you tried to delay all accesses to match. 99th percentile latencies on modern systems are absurdly bad.
Oh, is it? (Why?) I suppose you could go for more like 95th percentile and, if it takes longer, freeze the entire pipeline until ready, along with the cycle counter. A deterministic cycle count is good enough for benchmarking even if it doesn’t actually represent real time.
The DDR retraining creates a massive latency spike, during which all memory accesses are halted. Modern systems are usually fast, except when they're not, and then they're hilariously slow.
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