The "waitstate count" idea smells to me. This seems like a VRAM bandwidth issue, so if the CPU has to "slot in" between display controller accesses (which would naturally take priority) then I would expect wait states to be *variable* depending on when CPU accesses land? @endrift
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I was thinking this too, a waitstate count seems exceptionally unlikely for hardware, a memory arbiter that can halt the CPU on simultaneous access seems most likely.
Waitstate count only makes sense to me if there is a hardware line buffer, so the display controller renders faster, and they actually have the CPU take priority. Then they could precompute consistent wait states such that they guarantee display is on time. Seems convoluted tho.
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is it? It seems to make sense to me: You need a buffer to render sprites to, you probably need one for the fancier bgs that require several fetches. Wouldn't be *too* surprised if color math/compositing/mosaic used one too, and then scan that one out. At least 2 seems plausible
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