The "waitstate count" idea smells to me. This seems like a VRAM bandwidth issue, so if the CPU has to "slot in" between display controller accesses (which would naturally take priority) then I would expect wait states to be *variable* depending on when CPU accesses land? @endrift
(obviously the infinite waitstates case means the CPU gets no bandwidth at all, but I fear the other cases may not be cycle-accurate with the current approach?)
