Hector Martin

ughhh and it's still consistent if i use my old apio install to build the working and broken verilog files. i could see how the order might break initialisation of idx, but the fact that i still get 8 bytes out (they're just all zeroes) makes that seem wrong?

very annoyed that my design worked /perfectly/ in hardware... once. cannot for the life of me get it to work again

fpga people! what should i be assuming if with randomly seeded synthesis runs my design always happily passes timing by a 20 MHz margin, but randomly fails (i.e. for a particular bitstream, either always works through multiple resets or never works through multiple resets)

basically i'm asking "where should i be looking for issues"

it doesn’t seem like a physical wiring issue, since i’d expect that to show variability between resets, and it doesn’t seem like an issue with my code, since it’s unchanged between synthesis runs

oh! i also don't expect it to be a skew issue, since the spi clock frequency is on the order of 100 kHz and obviously that gives basically a whole half cycle of hold time