Hector Martin

my current best guess is that the rolloff happens because it turns off high side drivers while idle and relies on pull resistors to maintain the level; but it's still a CMOS output because it has fast rising/falling edges not sure why though, lower static power?

you can see it in the waveform but I should mention it explicitly too: this is -supposed- to be a completely ordinary 3.3 V TTL UART, it does -not- have a charge pump anywhere, or at least isn't supposed to. this is -not- RS-232

the best hypothesis so far is that the chip designers went for a multidrop UART that would only exhibit a bus conflict for a very short time, though I couldn't find any explicit mention of anything like that feature, or even any mention of half-duplexhttps://twitter.com/DSPonFPGA/status/1264739607180005378 …

thank you! brilliant find. I thought of looking at similar CPUs but missed this one

Isn't that for the synchronous serial controller though, not the UART? I don't see anything there related to this kind of feature for the UART.

This kind of drive is used in smart cards readers. The IO line of a smart card is open drain but for high data rates like f/d= 16 or 8, a pullup is not enough, so iso7816 drivers go push pull for a short time before letting it open drain. If not implemented right, can be a mess.

Consistent with the fact that the doc shows a bidir IO line.