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marcan42's profile
Hector Martin
Hector Martin
Hector Martin
@marcan42

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Hector Martin

@marcan42

If it ain't broke, I'll fix it! I'm porting Linux to Apple Silicon Macs at @AsahiLinux. http://patreon.com/marcan  | http://github.com/sponsors/marcan 

Tokyo, Japan
marcan.st
Joined May 2009

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    1. whitequark‏ @whitequark 24 May 2020
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      EE followers: do you have a good idea why an UART would behave like that? i.e. sharp edges but slow rolloff from rising to falling edge. please only reply if you're certain, i'm more than capable of guessing myselfpic.twitter.com/kuCqONlq66

      13 replies 7 retweets 60 likes
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    2. whitequark‏ @whitequark 24 May 2020
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      my current best guess is that the rolloff happens because it turns off high side drivers while idle and relies on pull resistors to maintain the level; but it's still a CMOS output because it has fast rising/falling edges not sure why though, lower static power?

      2 replies 0 retweets 17 likes
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    3. whitequark‏ @whitequark 24 May 2020
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      you can see it in the waveform but I should mention it explicitly too: this is -supposed- to be a completely ordinary 3.3 V TTL UART, it does -not- have a charge pump anywhere, or at least isn't supposed to. this is -not- RS-232

      3 replies 0 retweets 9 likes
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    4. whitequark‏ @whitequark 24 May 2020
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      whitequark Retweeted Muzaffer Kal @ 🏡  🇺🇸

      the best hypothesis so far is that the chip designers went for a multidrop UART that would only exhibit a bus conflict for a very short time, though I couldn't find any explicit mention of anything like that feature, or even any mention of half-duplexhttps://twitter.com/DSPonFPGA/status/1264739607180005378 …

      whitequark added,

      Muzaffer Kal @ 🏡  🇺🇸 @kal_muzaffer
      Replying to @whitequark
      is there any chance this is supposed to be a shared line? It's a standard trick where each side drives the line for a very short time then floats so if there is any conflict, it's very short. It might just be a bug which didn't get detected with IOs with lower leakage.
      2 replies 0 retweets 12 likes
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    6. whitequark‏ @whitequark 24 May 2020
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      Replying to @chrisfreder

      thank you! brilliant find. I thought of looking at similar CPUs but missed this one

      2 replies 0 retweets 2 likes
    7. Hector Martin‏ @marcan42 25 May 2020
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      Replying to @whitequark @chrisfreder

      Isn't that for the synchronous serial controller though, not the UART? I don't see anything there related to this kind of feature for the UART.

      1 reply 0 retweets 3 likes
    8. SΞbastien F4GRX‏ @f4grx 25 May 2020
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      Replying to @marcan42 @whitequark @chrisfreder

      This kind of drive is used in smart cards readers. The IO line of a smart card is open drain but for high data rates like f/d= 16 or 8, a pullup is not enough, so iso7816 drivers go push pull for a short time before letting it open drain. If not implemented right, can be a mess.

      1 reply 0 retweets 7 likes
    9. SΞbastien F4GRX‏ @f4grx 25 May 2020
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      Replying to @f4grx @marcan42 and

      Consistent with the fact that the doc shows a bidir IO line.

      1 reply 0 retweets 0 likes
      Hector Martin‏ @marcan42 25 May 2020
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      Replying to @f4grx @whitequark @chrisfreder

      TxD2 is not bidir though, but it is listed as hi-z during reset and the like, so clearly the "bidir" marking in the doc doesn't have much relevance to whether the driver has a high-z mode or not. TxD1 is bidir because it is shared with a GPIO.

      1:33 AM - 25 May 2020
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      • hell writes memory initialization code for fun SΞbastien F4GRX
      1 reply 0 retweets 2 likes
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        2. Hector Martin‏ @marcan42 25 May 2020
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          Replying to @chrisfreder @f4grx @whitequark

          Oh, missed that detail. Anyway yeah, it would have it due to the reset behavior either way. I wonder why the UART behaves like that though.

          0 replies 0 retweets 2 likes
          3. End of conversation

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