w-what happened to my L2 cache on the fourth of Aprilpic.twitter.com/61xL1XnADX
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the weird thing is that i dont recall seeing any main DRAM ECC errors; kinda worrisome and makes me think that maybe the motherboard/RAM/CPU combination isn't actually doing ECC :/
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There's no particular reason why DRAM ECC errors would be correlated. The reporting might be different, e.g. on AMD this goes through EDAC, not MCE, I think. And I'm not even sure if correctable errors are logged as MCEs.
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i imagined that if there's enough radiation dose to cause cache bits to flip that eventually i'd see a DRAM bit flip ;;
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Only a small set of angles intersect *both* your CPU *and* your DRAM chips :-) I'm told Google datacenter engineers could trace back the origin of cosmic rays by looking at ~simultaneous DRAM errors and looking at the physical location of those servers...
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