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you could produce a layered multi-PCB construction with a randomised protection grid within each multi-layer PCB the interruption of which would zeroise the microcontroller ... etc. etc. there are lots of possiblities here.
Then you need it to use battery-backed SRAM. Which is how high-end HSMs work, but kind of significantly increases the cost/complexity (and chance of losing the key material accidentally).
possibly, or a supercap w/ ultra-low power sram for seed material - or possibly flash memory encrypted with some PBKDF function over the PIN code + a random data in the OTP-rom in the micro.
or maybe even use a standard proprietary smart card chip via standard interfaces for decrypting seed/configuration data so that you can take advantage of their "hardened" properties without their software contaminating yours?
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