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AFAICT the mics are TDM mics in a stereo config (shared data line, idling at average of ~1/2 Vcc, don't have scope with me to check). That's connected to a single AND gate (SN74LV1T00 or equiv), the other input comes from the mute switch.
When the mute is engaged, the output of the gate drops to 0V, and that is what goes to the SoC (after a divider, the SoC is probably 1.8V logic while the mics/AND are at 3.3V).
I traced the path from the hardware switch, through a filter/debounce network, to the AND gate, and from the mics to the AND gate. So unless there are backdoor buried traces that bypass this (which would be hard evidence of a backdoor, since they would make *no sense*), it's safe
(correction, I meant PDM mics, not TDM; TDM is a different style, though PDM mics do time-division-multiplex the stereo channels, which is how I mixed it up)
I have only read your tweets about this, so maybe the question is stupid, but here it is: is the AND control gate software driven? Or is it connected directly to a hardware switch? Because if software driven, the mute function is still software driven.
The next tweet notes the direct path from the switch to the AND gate.https://twitter.com/marcan42/status/1186110966984916994?s=19 …
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