Hector Martin

Maybe @ben_eater, @eevblog, @benheck would know :)

/cc @marcan42 for FPGA wizardry

The answer is yes, it matters just like on an FPGA, and you can certainly get into sticky situations with setup/hold times. But as long as all your logic is the same type it should work well together in the slow case, and then it's just a matter of how high you can clock.

Discrete logic designs are rarely run at anywhere past a MHz or two, while FPGA designs are often pushing 100MHz. It's also much harder to simulate a physical circuit to come up with a theoretical timing model, because you don't know things like wire capacitance.

On an FPGA the physical layout is fairly uniform and you can derive a "safe" timing model that is consistent (in practice you can often go much faster than the timing report says, but no guarantees). With breadboard designs, well, just try and see.

Even at slow clocks though, you can definitely have timing and signal integrity problems. For example, bad clock routing can cause ringing/reflections and double-clocking of logic. In general mixing fast and slow logic can be a bad idea.

If you use fast logic then it's going to have fast rise/fall times, and that higher dV/dt can cause problems with clocks or clock-like signals if the signal integrity is not up to par. Slower buffers can mitigate this at the expense of being, well, slower.

Of course you can mitigate this with things like well placed resistors to limit current and thus rise times; sometimes adding capacitance helps too.