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/cc @marcan42 for FPGA wizardry
The answer is yes, it matters just like on an FPGA, and you can certainly get into sticky situations with setup/hold times. But as long as all your logic is the same type it should work well together in the slow case, and then it's just a matter of how high you can clock.
Discrete logic designs are rarely run at anywhere past a MHz or two, while FPGA designs are often pushing 100MHz. It's also much harder to simulate a physical circuit to come up with a theoretical timing model, because you don't know things like wire capacitance.
On an FPGA the physical layout is fairly uniform and you can derive a "safe" timing model that is consistent (in practice you can often go much faster than the timing report says, but no guarantees). With breadboard designs, well, just try and see.
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