To wrap up the QLC saga: Crucial P1 SSDs (QLC) peaking at >50% IO usage, >1s long tail latencies, cluster fell over under load, HDDs faster (!) Samsung 970 Evo Plus SSDs (TLC) peaking at ~3% IO usage, <10ms long tail latencies, cluster *very* happy. Stay away from QLC.
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Point is that all flash cells fail with a given probability, right, and "fail" might be a relative term already, since multilevel flash cells exhibit threshold voltage aging. So the question is what error coding and decoding a controller does, and how smart it is at compensating.
This happened on 10 different brand new units at fairly low usage and >50% of the space totally untouched. It's not an aging thing. It didn't even have enough writes to program each page more than once.
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Hm, that's interesting, and it indicates that QLC controllers might not be mature enough (can you list the designers of the controllers, not just the SSD as whole?). Generally, it's mostly a matter of cost: With QLC (misleading name, btw) you get 33% more bit per area than TLC…
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… which reduces your cost. Of course, your cell error rate on the other hand increases, but you counter that by more involved error coding, which of course requires more redundancy, so you don't get the net 33% capacity gain. I'd still, in total, expect SSDs to be designed so…
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