To wrap up the QLC saga: Crucial P1 SSDs (QLC) peaking at >50% IO usage, >1s long tail latencies, cluster fell over under load, HDDs faster (!) Samsung 970 Evo Plus SSDs (TLC) peaking at ~3% IO usage, <10ms long tail latencies, cluster *very* happy. Stay away from QLC.
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Got a detailed writeup on your findings somewhere? This *really* much sounds like a bad controller design problem (not itself caused by the number of bits per cell, but by the way they are reconstructed on reading, or maybe how they are written), and that'd be where suppliers 1/2
Firmware is definitely part of the problem (especially the 1 second latencies), but QLC flash having terrible performance (hidden by a TLC/MLC buffer that fills up quickly) is a thing.
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Point is that all flash cells fail with a given probability, right, and "fail" might be a relative term already, since multilevel flash cells exhibit threshold voltage aging. So the question is what error coding and decoding a controller does, and how smart it is at compensating.
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And the latter, compensating threshold shifting w/ usage, requiring fine analog circuitry, suggests this is not a firmware,but a (potentially pretty cost-intense)controller HW problem first & if I had to take a guess, a flash controller doesn't error decode in firmware, either.
End of conversation
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