Thunderclap: "As far as we can ascertain, Xilinx, Lattice and Intel Cyclone FPGAs don’t allow us to replace the vendor-supplied implementation of configuration registers with our own (Intel calls it ‘config bypass’ mode) which we require."
And yet we made it work on Lattice 
Xilinx uses hard IP for PCIe as far as I know (on the FPGAs I've looked at) and it doesn't give you enough control. You need to write your own PCIe core from scratch and just use the SERDES part.
-
-
This Tweet is unavailable.
-
Heh, yeah, we might've been looking at 6 series at the time.
End of conversation
-
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.