Hector Martin

Thunderclap: "As far as we can ascertain, Xilinx, Lattice and Intel Cyclone FPGAs don’t allow us to replace the vendor-supplied implementation of configuration registers with our own (Intel calls it ‘config bypass’ mode) which we require." And yet we made it work on Lattice

(this may or may not have required some unorthodox hacks though *cough*)

This is basically possible anywhere where you can use a soft PCIe core, which I think is most FPGAs, though e.g. on Xilinx you'd need to reimplement everything but the SERDES in the fabric and ignore the PCIe hard IP block which is what you'd normally use.