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This is basically possible anywhere where you can use a soft PCIe core, which I think is most FPGAs, though e.g. on Xilinx you'd need to reimplement everything but the SERDES in the fabric and ignore the PCIe hard IP block which is what you'd normally use.
That said, props to Thunderclap folks for making a proper productionized/weaponized platform for PCIe device impersonation (our PS4 thing was a single-purpose duct-taped pile of hacks).
What do you mean with "duct-taped"??!! We had an, erm, "forcibly open-sourced" PCIe core, TLP-over-UART (+Ethernet backchannel), piped into a realtime Python process that sometimes system()'ed out to a script poking into /dev/mem - what part exactly was duct-taped, eh?!
Look I'm pretty sure duct tape was involved in the wiring job at some point, like, literally.
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