(this may or may not have required some unorthodox hacks though *cough*)
Show this thread
Thunderclap: "As far as we can ascertain, Xilinx, Lattice and Intel Cyclone FPGAs don’t allow us to replace the vendor-supplied implementation of configuration registers with our own (Intel calls it ‘config bypass’ mode) which we require."
And yet we made it work on Lattice 
-
-
-
This is basically possible anywhere where you can use a soft PCIe core, which I think is most FPGAs, though e.g. on Xilinx you'd need to reimplement everything but the SERDES in the fabric and ignore the PCIe hard IP block which is what you'd normally use.
Show this thread -
That said, props to Thunderclap folks for making a proper productionized/weaponized platform for PCIe device impersonation (our PS4 thing was a single-purpose duct-taped pile of hacks).
Show this thread
End of conversation
New conversation -
-
-
I’ve done it on Xilinx
-
I think they meant to say "Intel, lattice and cyclone *PCIe blocks* don't allow us" which afaik is true, especially if you want to release your code.
- Show replies
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.