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I might be able to find some time to publish the tools and methods I used based on a standard logic analyzer (no fpga). Would anyone find that useful/interesting?
I was using my FPGA as a logic analyzer (literally just dumping out LPC bus cycles as bytes, 5 bits per sample, LFRAME + LAD[0:3]), 180 of lines of C to parse that into LPC transactions, and 30 lines of Python to parse those into TPM messages. It's all pretty trivial.
