Hector Martin

It’s 100% about when you check privileges in the TLB access pipeline. If you check eagerly you are fine, lazily —> Meltdown.

What I mean is the problem isn't the TLB itself, it's what you do with the data when the TLB hits but you don't pass the privilege check. They should be eagerly dropping/poisoning it instead of steamrolling forward on privileged data.

That’s true. But how much was that timing impact when the design was first done? It’s pretty rude to call the CPU designers idiots for a reasonable decision taken by many different teams. Especially when you don’t understand the trade-offs involved 1/N

@jonmasters made a good point that the lack of communication between SW and HW is a cause of the security problem. Understanding why the decision was made is probably a good idea, rather than assuming incompetence or idiocy. 2/N

Are DRAM designers morons for allowing rowhammer? That hasn’t been solved, whereas Meltdown has. The only solution I’ve heard for rowhammer is “let’s make DRAM way more expensive”. The future isn’t SW or HW, it’s systems architecture spanning both and less tribalism! N/N

Rowhammer is Intel's fault too: they're largely the reason why desktop systems do not use ECC memory (because they market it as premium). It is utter insanity that at current DRAM densities we pretend memory is flawless. Every other storage tech has used ECC for decades.

ECC would increase DRAM costs by at least 11%. Notice how it isn’t used in phones and many embedded devices? 200M PCs, $30/PC —> you want to spend $600M in BOM and $1.2B in consumer prices *annually* to “help” and not solve a problem? That sounds like poor economics.

Mitigating via smarter controllers is a much better approach, but it only helps and doesn’t solve :( Physics is an unforgiving enemy...