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It’s 100% about when you check privileges in the TLB access pipeline. If you check eagerly you are fine, lazily —> Meltdown.
What I mean is the problem isn't the TLB itself, it's what you do with the data when the TLB hits but you don't pass the privilege check. They should be eagerly dropping/poisoning it instead of steamrolling forward on privileged data.
Of course, it takes a very special kind of idiocy to not only do that but *also* use garbage address data on nonpresent pages *and* short-circuit EPT while you're at it, which is L1TF and an Intel exclusive.
Intel is terrible at security. when your hardware is more secure with the security features like ME disabled it says all you need to know about sloopy security
That’s true. But how much was that timing impact when the design was first done? It’s pretty rude to call the CPU designers idiots for a reasonable decision taken by many different teams. Especially when you don’t understand the trade-offs involved 1/N
@jonmasters made a good point that the lack of communication between SW and HW is a cause of the security problem. Understanding why the decision was made is probably a good idea, rather than assuming incompetence or idiocy. 2/N
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