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And yes, Spectre v1 and PortSmash aren't going away. Anyone who knows anything about CPUs knew PortSmash was theoretically possible for years (just someone bothered to finally implement it). Disable HT or petition OSes to do security-domain-aware HT by default.
Also PortSmash should be adaptable to AMD systems with HT (i.e. Zen) and also all the POWER stuff. And it gets worse, because under more specific circumstances and with cleverer exploits, the side channels go beyond HT and to shared caches too.
Ultimately, computing needs to come to terms with the fact that any time there is *any* shared resource, that's ripe for side channels. This includes main memory and peripheral devices. It's worse and more insidious the lower level and more tightly coupled you make it, like HT.
NUMA NUMA yay?
They arn’t going away as in future processors might still be susceptible?
As in they *will* be susceptible. It's inherent. They cannot be fixed without killing performance.
But the Intel decided DDIO allowing the NIC to write directly into L3 cache was a good idea… ¯\_(ツ)_/¯
Sparc has (had ?) up to 8 threads per core.
Well, "should" means nobody could proof it in any way yet, and could also mean they are not affected at all.
No, they *will* be affected. It's fundamental to how HT works.
I wonder if this could be adopted to the Niagara T1/T2. So far they were unaffected by every Spectre and similar variant. That would be the first thing.
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