Aaand suddently VM-exit latencies on Intel CPUs will go through the roof, oh, and if you're still putting different guests on sibling hyperthreads you're going to get pwned and you know it. Good job, Intel. You saved a few AND gates. Was it worth it? https://www.redhat.com/en/blog/understanding-l1-terminal-fault-aka-foreshadow-what-you-need-know …
But it didn't occur to people... because they weren't working in both fields. The problem isn't speculation, it's speculation + side channels. HT was always dangerous, but the cache side-channels are just something nobody thought through properly.
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The thing is that speculation is really too good to pass up. Can you imagine how slow a loop not using a register would be overwise? At current frequencies, we’re probably talking 10-50x slowdown. The proper fix (AMDs) likely makes context switches non-trivially slower.
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There is No Good Solution™ to the general speculation problem (Spectre v1) other than to use barriers in security-sensitive code (and teach people about them), but v2 and meltdown and now this are absolutely fixable in silicon with negligible performance impact.
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As for cache side channels, they suck but are merely an attack vector. That you need a way to exploit the bug doesn’t mean the exploit vector is the core problem, there are too many potential other ways to leak data
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Yes, the issue is that nobody considered the existence of those side channels. This whole saga is basically CPU manufacturers discovering that timing side channel attacks apply to them as well.
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