320ns for a random DDR3 DRAM read means design changes will need be necessary to keep up with even the slowest PCH SPI bus speed of 17MHz.pic.twitter.com/GjbP1PnkWk
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320ns sounds terrible; I did some worst case back of the napkin calculations for SDRAM and even with a refresh cycle in the way it should be in the 100ns ballpark. Access times haven't improved with DDRx but they haven't gotten worse either.
FWIW I'm trying to solve a similar problem (but haven't prototyped it yet): async parallel ROM emulation with SDRAM.