320ns for a random DDR3 DRAM read means design changes will need be necessary to keep up with even the slowest PCH SPI bus speed of 17MHz.pic.twitter.com/GjbP1PnkWk
320ns sounds terrible; I did some worst case back of the napkin calculations for SDRAM and even with a refresh cycle in the way it should be in the 100ns ballpark. Access times haven't improved with DDRx but they haven't gotten worse either.
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FWIW I'm trying to solve a similar problem (but haven't prototyped it yet): async parallel ROM emulation with SDRAM.
Thanks. Twitter will use this to make your timeline better. UndoUndo
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Separating the page open from the read might improve the timing enough to make this work for SPI flash. I'm testing with the OpenArty migsdram.v, which adds yet another layer (Wishbone to AXI to MIG) and doesn't expose them individually.https://github.com/ZipCPU/openarty/blob/master/rtl/migsdram.v …
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Yeah, I'm considering a carefully optimized SDRAM controller here. If you just use a generic one it's going to have worse latency and also less predictable (e.g. refresh cycles will mess you up randomly).
End of conversation
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