@jedisct1 @cryptocephaly Or is it needing (and lacking in hw) carry-less multiplication? This isn't my field, I am just curious.
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@jedisct1@cryptocephaly I skimmed over this paper the other day, found it curious the hardware 18x18 multipliers aren't even mentionedThanks. Twitter will use this to make your timeline better. UndoUndo
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@jedisct1@cryptocephaly Is pipelining assumed to be of such much benefit that the hardware multipliers are inferior for this use case?Thanks. Twitter will use this to make your timeline better. UndoUndo
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@jedisct1@cryptocephaly Can't do 3 clock cycles for this size using just an 18x18 primitive, but could higher(?) clock rate compensate?Thanks. Twitter will use this to make your timeline better. UndoUndo
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@jedisct1@cryptocephaly I assume it was sound judgment to build the LUT-based multipliers, but I'd be curious in a comparison vs. 18x18'sThanks. Twitter will use this to make your timeline better. UndoUndo
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