looking at "Round 2 Candidates" in NIST's Lightweight Crypto project, surprised to observe that many designs have
1) a state larger than that of AES
2) an invertible key schedule (on embedded platform you want to avoid this)
this is a teaser for @diagprov's talk in DC :)
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hardware size is often referred to as a limitation (I'm not saying it is): to store N bits you typically need as many flip-flops which occupy between 5N to 10N gate-equivalent depending on the technology.. look at Grain or Trivium, most of the area is just storing bits, not logic
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disclaimer: I'm not a hardware designer, haven't worked with hardware engineers lately, hardware people please correct my claims if needed
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