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jedisct1's profile
Frank
Frank
Frank
@jedisct1

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Frank

@jedisct1

France
Joined November 2008

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    Frank‏ @jedisct1 21 Oct 2019
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    LLVM provides no side-channel resistance https://dsprenkels.com/cmov-conversion.html …

    5:45 PM - 21 Oct 2019
    • 33 Retweets
    • 81 Likes
    • Eugene Oskin Jonas Malaco Diego F. Aranha 🕷️ Le Quoc Viet Roeland de Vries Normand Aurélien 🐙 Arvid E. Picciani 🚗⚡♻️⧖ Alyssa Rowan Skyedelaciel 🏳️‍🌈 🔜 HuskyX!!!!
    5 replies 33 retweets 81 likes
      1. New conversation
      2. geggleto‏ @geggleto 22 Oct 2019
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        Replying to @jedisct1

        definitely like the idea of the language keyword for secrecy. I hope some languages choose to do that.

        2 replies 0 retweets 4 likes
      3. Daira Hopwood (abolish ICE)‏ @feministPLT 14 Nov 2019
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        Replying to @geggleto @jedisct1

        Daira Hopwood (abolish ICE) Retweeted Daira Hopwood (abolish ICE)

        https://twitter.com/feministPLT/status/1195082918315646976 … (Noether was never implemented, but I intend to get back to it in the not-too-distant future.)

        Daira Hopwood (abolish ICE) added,

        Daira Hopwood (abolish ICE) @feministPLT
        The suggestion of a compiler-supported "secret" annotation is similar to something I suggested, with credit to @zooko, in my presentation at Strange Loop 2013 (sides at https://github.com/noether-lang/noether/blob/master/doc/presentations/StrangeLoop/noether.pdf …). https://twitter.com/jedisct1/status/1186443466861088769 … pic.twitter.com/tSdiGXmLM0
        1 reply 1 retweet 16 likes
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      2. Andrew Zonenberg‏ @azonenberg 14 Nov 2019
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        Replying to @jedisct1

        IMO until CPUs have a means to provide guaranteed deterministic timing for a certain code path (specified in the ISA to be constant time even on future uarches) we're going to be chasing side channel issues at all levels of the HW/SW stack.

        1 reply 0 retweets 3 likes
      3. Andrew Zonenberg‏ @azonenberg 14 Nov 2019
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        Replying to @azonenberg @jedisct1

        The only way I'm aware of to be *certain* there are no timing side channels is to implement the relevant crypto functionality in a HDL and compile to ASIC gates or FPGA LUTs, with cycle-accurate deterministic timing.

        1 reply 0 retweets 3 likes
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      2. Deian Stefan‏ @deiandelmars 21 Oct 2019
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        Replying to @jedisct1

        Nice! We were working on a simple translation validation checker that you can run between passes to make sure that secret things are not suddenly used in branches or memory indexes. Having secret annotations in LLVM would be great! (I’m more worried about lowering to x86 though.)

        3 replies 0 retweets 5 likes
      3. Veelasha Moonsamy‏ @veelasha_m 21 Oct 2019
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        Replying to @deiandelmars @jedisct1

        cc @dsp6s

        0 replies 0 retweets 0 likes
      4. End of conversation
      1. Dave Hudson‏ @hashingitcom 14 Nov 2019
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        Replying to @jedisct1

        Deterministic CPUs are entirely possible (Qualcomm now own this design). We had designed this one to allow software to meet precise hardware timing specs and had hard real-time scheduling of the pipeline (including branches): http://www.texim-europe.com/getfile.aspx?id=68543 …

        0 replies 0 retweets 1 like
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      1. Conrado Gouvea‏ @conradoplg 22 Oct 2019
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        Replying to @jedisct1 @cryptojedi

        Does any other compiler? Using == is known to be bad for side channel resistance... (Though I totally agree we need better tooling)

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