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Currently working on
#synpathic, a graphical user interface for#yosys. As a teaser, here is the screenshot of a first prototype. I am implementing the following features: Simple project management, an editor pane, a schematic viewer, a#yosys shell, and a system shell. pic.twitter.com/467A0MOM3p
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Got some MACRO11 code running on the 1801vm2, of course powered by
#yosys &#icestormpic.twitter.com/ci8O09wzco -
Formal verification using
#yosys is so much fun! Who would've known. Found several issues in my brainfuck toy cpu. Induction mode found some interesting edge cases as well.Prikaži ovu nit -
My new Vivado 2017.4 favourite meme
#yosys@oe1cxw@ico_TC@fpga_davepic.twitter.com/NxspidSuLp
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Things I want for XMAS: 1) VHDL front-end for
#Yosys. 2) Formal verification support for above. 3) Verilog netlist -> schematic generator. 4) Better OSS ASIC place & route with timing/clock-tree gen. 5) To get paid for making 1, 2, 3 or 4. -
I just learned that
#yosys has a built-in netlist visualizer. I tried it out on the ice40-ported ay38500, which is appears as scattered logic along with several denser regions corresponding to the chip's counters... pic.twitter.com/tRPXn4cnxM
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First blinky on ECP5 EVN board :)
#yosys#prjtrellis#nextpnr#openocd@ico_TCpic.twitter.com/gURADZqnld -
Happy to announce that
#pyosys was merged into the master branch of#yosys: https://github.com/YosysHQ/yosys/commit/99d5435650c38fb96dc364c0fd4ac6250a4871ea … It is now possible to access#yosys data structures in a#Python session, and to call#yosys passes written in#Python. We presented#pyosys at#OSDA'19: https://osda.gitlab.io/19/index.html#3.3 … -
Decided to run
@fpga_dave's ice40 NES port on the ecp5-evn board :) and the pixel smoothing is working :)#opensource#fpga#nextpnr#yosys pic.twitter.com/6YpTjWOnI4
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New feature:
#verilog error detection in#Icestudio!#IcarusVerilog#Yosys#FPGAwarshttps://youtu.be/Cv_ZxP_pJvs -
MMC3 mapper support for iCE40 NES :) thanks again
@fpga_dave for laying the foundations, so I can play around :)#opensource#yosys#openfpgapic.twitter.com/CcGdHJZ2G7
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Tomorrow I will be presenting "Everything Wrong with FPGAs" at
@xdc2019. Watch and hopefully learn. Thanks for input from@ZirconiumX and@fpga_dave. Especially thanks to the#yosys project. -
Added one more mapper and expanded to the total 512Kb of sram on the
@Olimex iCE40 fpga board. All with open source tools#icestorm#yosys#nextpnrpic.twitter.com/63wBD6xKDV
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Released
#apio 0.4.0b1!
A beta version with experimental support for 6 new UP5K boards! Thanks @micko_mame for his awesome work!. Using latest#icestorm,#arachnepnr,#yosys#FPGAwarshttps://github.com/FPGAwars/apio/pull/153 … -
Indeed, this really is the mindset for turning this issue to the right way. We need
@arduinoteam to be aware of#yosys and explain what good can come if they will be part of It! -
Today I ignore my pass over my wonderful
#yosys toolchain and instead install the likely less-wonderfull and closed source Quartus. Because of a Cyclone V. Well, I'm also installing KiCAD at the same time, so I guess that balances stuff out... -
Just got ICE40 UltraPlus $8 board from Texas. http://www.gnarlygrey.com/development-platform.html#upduino … Time to make
#Yosys#IceStorm support for it.pic.twitter.com/WAH2aIrKJb
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