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Secondo la società di ricerca
#Semico, le vendite di core#RISC_V cresceranno rapidamente raggiungendo i 62,4 miliardi di core entro il 2025.@risc_v#opensource http://bit.ly/38YXNwP pic.twitter.com/CpWm0mXvR0
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Stay tuned on
@hipeac conference in Bologna Jan 20-22, several world-class#RISC_V related talks including@Calista_Redmond's,#openhardware#LOCA initiative from@BSC_CNS, and a tutorial on the current status of the@EuProcessor#EPIproject (I am one of the speakers
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NSITEXEがRISC-Vベースのプロセッサとして世界初となる、ISO 26262 ASIL D対応の車載向けプロセッサ「DR1000C」を発売 https://nsitexe.com/archives/676
#RISC_V#NSITEXE#Denso#DFP#Automotive -
Bluespecが独自の高抽象度設計言語Bluespec SystemVerilog(BSV)を用いたハード設計ツールをオープンソース化 https://bluespec.com/2020/01/06/bluespec-inc-to-open-source-its-proven-bsv-high-level-hdl-tools/ …
#Bluespec#RISC_V#HLS -
Four RISC-V presentations from
@HotChipsOrg 31 (@KAsanovic, Bunnaroath Sou,@ZheMao & Jerry Zhao,@FabianSchuiki; 2019, 3 hours):
https://youtu.be/nPXdbm9lc3A
https://www.hotchips.org/archives/2010s/hc31/ …
#SoC#ISA#RISCV#RISC_V#ComputerEngineering pic.twitter.com/aNJ701ZDuK
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@zGlue collaborated with@antmicro and partners to release rapid turnaround chiplet-based#ASIC called GEM at RISC-V Summit! Read more at: https://zglue.com/blog/antmicro-gem …#GEM#zGlue#Antmicro#RISC_V#RISCV#UnleashRISCVpic.twitter.com/USN68PF0YD
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“bpf-jit-verif” is a tool to run formal verification of the
#eBPF#RISC_V JIT-compiler, based on the Serval framework, by@lukenels_ and Xi Wang. Hopefully more architectures will be supported in the future!https://github.com/uw-unsat/bpf-jit-verif … -
11/27に北京でRISC-Vのイベントあるから誰か行くといいよ。ワイは貧乏だからいけない


#RISC-V#RISCV#RISC_V pic.twitter.com/dOH53KMVd8
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中国国産のRISC-V開発用IDE登場。 その名も「Riscv IDE」 (検索性悪すぎない?) http://www.compiler-dev.com
#RISCV#RISC_V#卡姆派乐#RiscvIDEPrikaži ovu nit -
#IARDevCon is happening in#Boston! " “As digital technology and even more smart products continue to spread the market for embedded systems is in a state of constant change.”#risc_v@iarsystems#iot#iiot#ml#security#automotive#industry40 --> https://iardevcon.com/ pic.twitter.com/EtznASHZ9k
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RISC-V デバッグサポートマニュアルの日本語訳、★★★ 94頁すべて訳し終わりました。★★★。 riscv-debug-release_v0.13.2_jp.pdf https://github.com/shibatchii/RISC-V …
#RISCV#RISC_V#RISC-VPrikaži ovu nit -
RISC-V デバッグサポートマニュアルの日本語訳、第5章 5.2.1 5.2.1トリガー選択(tselect、0x7a0)まで訳した。おおよそ2/3位まできた。 riscv-debug-release_v0.13.2_jp.pdf https://github.com/shibatchii/RISC-V …
#RISCV#RISC_V#RISC-V -
The
#opensource wave at@ETH Zurich is building up!#RISC_V topics continue today and Friday at the Week of Open Source Hardware#WOSH we’re proud to be co-sponsoring!@FoSSiFoundation@RISC_V@lowRISC: https://fossi-foundation.org/wosh/ pic.twitter.com/obA1dkdIUP
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The Week of
#OpenSource#Hardware (#WOSH) kicking off with the#risc_v workshop. https://fossi-foundation.org/wosh/#HPC@pulp_platform@FossiFoundationhttps://twitter.com/lowRISC/status/1138346483240046592 …
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The unmistakable silhouette of
@UltraSoC's Gadge Panesar kicks off the Bristol#RISC_V meetup at@DeskLodgeBRSpic.twitter.com/PvBeDiOTgs
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It's our
#Bristol#RISC_V@Meetup co-hosted with@ImperasSoftware 2moro, Tuesday@DeskLodgeBRS. Not too late to register! Join us for some live demos, and interesting talks including@Huawei@CerberusLabs@BristolUni https://www.ultrasoc.com/event/bristol-risc-v-meetup-2/ …pic.twitter.com/ODZMxhrKYr
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Latest news
: FreeRTOS now officially supports #RISC_V. And guess what, one of the preconfigured examples includes the VEGAboard with PULP inside! Learn more: https://aws.amazon.com/it/blogs/aws/new-risc-v-support-for-freertos-kernel/ …https://www.freertos.org/RTOS-RISC-V-Vegaboard_Pulp.html … -
7 days remaining for intense project finishing phase. The 4 SHP-ed
#RISC_V (RV32iMC) cores fit nicely onto the ARTY FPGA using HI-guided floorplaning. Having fun with register balancing the next days to squeeze out the last ns. Not having fun with docu. pic.twitter.com/5ae3qJjohj
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The
#eBPF JIT-compiler for#RISC_V, by@bjorntopel, has just been merged into the Linux kernel. https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git/commit/?id=90d304b7f7a1c9ab6cdce54d65c55e5c722f0d25 … -
We're delivering on our promise to open source the SweRV core: http://wdc.li/6018EPcT4
#opensource#riscv#risc_v pic.twitter.com/1OlARMSnOR
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