Rezultati pretraživanja
  1. 10. pro 2019.
  2. 10. pro 2019.

    “Don’t build it alone, leverage the community! This is what Open Source is about” Martin Fink

  3. Love seeing the whole team having a huddle before show open at ! If you're at the show make sure to go see them at booth 205.

  4. 11. pro 2019.

    Curiously I haven’t heard anyone mention at the that ’s new CrossLink comes with two 32-bit ALU&RF hardblocks. I thought that was a pretty interesting addition and look forward to hearing more.

    Prikaži ovu nit
  5. 11. pro 2019.

    The place to be today! RISC-V Summit.

    Prikaži ovu nit
  6. 11. pro 2019.

    A PULP-related talk coming soon at the 😊. At 4:40 p.m. Matheus will be presenting his work on the vector processor Ara.

  7. 5. pro 2019.

    Are you going to the in San Jose next week? There’ll be a number of seL4 activities: My talk "seL4 on RISC-V: Verified OS for True Security” Wed 1.50pm, the DornerWorks tutorial "seL4 on RISC-V Renode”, and a poster from the seL4-US CoE

  8. 10. pro 2019.

    Interesting: Samsung is using cores in its 5G mmWave RF, due to ship in "flagship" phones in 2020 and AI image sensors

  9. 10. pro 2019.

    Congratulations to for receiving a Director's Award for his work on RISC-V especially the formal specification. Well done!

  10. 10. pro 2019.

    ⁩ on future proofing ⁦⁩ across hardware and software

  11. 11. pro 2019.

    And here comes Rick's talk on his big hairy plans with the 😊. PULP inside.

  12. 11. pro 2019.

    Day 2 starting now with a welcome from kicking off another day of tech talks!

  13. 9. pro 2019.

    Tomorrow is the first day of the - don't forget to stop by the Dover Microsystems poster in the poster gallery and talk with our co-founder & Chief Scientist, Greg Sullivan

  14. 10. pro 2019.

    Risc-V state of the union with at the RiscV Summit.

  15. 11. pro 2019.

    Thumbs up for EPI Poster at the RISC-V Summit 2019😃👍 Nick Kossifidis from discussing with , CEO of the RISC-V Foundation and Jeffrey Osier-Mixon from the Linux Foundation

  16. 10. pro 2019.

    NSITEXE licensed our TileLink VIP for complete verification of its hi-efficiency, hi-quality semi IP adaptable to various applications using RISC-V architecture. Visit our booth at to find learn more. Contact us at demo@smart-dv.com.

  17. 13. pro 2019.

    And this is Francesco, another new PhD student, presenting his huge poster at the in San Jose. The project is the Klessydra Orbital Lab, a pocketcube satellite equipped with an on-board computer based on a Klessydra fault-tolerant core on FPGA.

  18. 11. pro 2019.

    Thank you for a great keynote at the .

  19. 11. pro 2019.

    It's great to see mentioned in the keynote today at the .

  20. 24. pro 2019.

    At this year's , announced it is using SiFive's RISC-V cores for various upcoming chips. Anandtech wrote about it here:

Čini se da učitavanje traje već neko vrijeme.

Twitter je možda preopterećen ili ima kratkotrajnih poteškoća u radu. Pokušajte ponovno ili potražite dodatne informacije u odjeljku Status Twittera.