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“Don’t build it alone, leverage the community! This is what Open Source is about” Martin Fink
@westerndigital@risc_v#RISCVSummit pic.twitter.com/baeYdHNpzN
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Love seeing the whole
@MicrochipTech team having a huddle before show open at#RISCVSummit! If you're at the@risc_v show make sure to go see them at booth 205.pic.twitter.com/kHSZraeGZe
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Curiously I haven’t heard anyone mention at the
#RISCVSUMMIT that@latticesemi’s new CrossLink#FPGA comes with two@risc_v 32-bit ALU&RF hardblocks. I thought that was a pretty interesting addition and look forward to hearing more.Prikaži ovu nit -
The place to be today! RISC-V Summit.
#RISCVSummitPrikaži ovu nit -
A PULP-related talk coming soon at the
#RISCVSummit
. At 4:40 p.m. Matheus will be presenting his work on the vector processor Ara. pic.twitter.com/qkperkhWOU
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Are you going to the
#RISCVSUMMIT in San Jose next week? There’ll be a number of seL4 activities: My talk "seL4 on RISC-V: Verified OS for True Security” Wed 1.50pm, the DornerWorks tutorial "seL4 on RISC-V Renode”, and a poster from the seL4-US CoE -
Interesting: Samsung is using
@risc_v cores in its 5G mmWave RF, due to ship in "flagship" phones in 2020 and AI image sensors#RISCVSummit pic.twitter.com/9zAxZSdd0p
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Congratulations to
@RSNikhil for receiving a Director's Award for his work on RISC-V especially the formal specification. Well done!#RISCVSummit pic.twitter.com/MBmhqIROY4
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@kasanovic on future proofing @risc_v across hardware and software#RISCVSummit pic.twitter.com/siONJfNkoK
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And here comes Rick's talk on his big hairy plans with the
@openhwgroup
. PULP inside. #RISCVSummit pic.twitter.com/9XB2CI1uRH
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Day 2 starting now with a welcome from
@Calista_Redmond kicking off another day of tech talks!@risc_v#RISCVSummit pic.twitter.com/vp9OLBKMPA
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Tomorrow is the first day of the
#RISCVSummit - don't forget to stop by the Dover Microsystems poster in the poster gallery and talk with our co-founder & Chief Scientist, Greg Sullivan -
Risc-V state of the union with
@kasanovic at the RiscV Summit.#riscv#riscvsummit pic.twitter.com/VRd29xWhZS
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Thumbs up for EPI Poster at the RISC-V Summit 2019

Nick Kossifidis from @FORTH_ITE@CarvForth discussing with@Calista_Redmond, CEO of the RISC-V Foundation and Jeffrey Osier-Mixon from the Linux Foundation@riscv#RISCVSummit#RISCVpic.twitter.com/LLvxPmersK
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NSITEXE licensed our TileLink VIP for complete verification of its hi-efficiency, hi-quality semi IP adaptable to various applications using RISC-V architecture. Visit our booth at
#RISCVSummit to find learn more. Contact us at demo@smart-dv.com. https://bit.ly/36nGLHj pic.twitter.com/llQ5BTsheJ
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And this is Francesco, another new PhD student, presenting his huge poster at the
#RISCVSummit in San Jose. The project is the Klessydra Orbital Lab, a pocketcube satellite equipped with an on-board computer based on a Klessydra fault-tolerant core on FPGA. pic.twitter.com/j8IXyjXmSG
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Thank you
@zbandic for a great keynote at the#riscvsummit. pic.twitter.com/SJpbGPOKXm
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It's great to see
@ZephyrIoT mentioned in the@openhwgroup keynote today at the#riscvsummit. pic.twitter.com/n9OAMWatzK
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At this year's
#RISCVSummit,@Samsung announced it is using SiFive's RISC-V cores for various upcoming chips. Anandtech wrote about it here: https://hubs.ly/H0mmFPL0
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