Rezultati pretraživanja
  1. Joel Sing just finished landing the RISC-V port to the almost-out 1.14! It works! 🎉 (We'd made a special exception to let the stuff land during the freeze since it was mailed prior to the freeze, sufficiently isolated, and distros/people were waiting on it.)

  2. Odgovor korisnicima i sljedećem broju korisnika:

    More importantly, the only way to get an open firmware device is to either use a slow FPGA variant or buy a small, low power chip that the silicon vendor had to be embarrassed into releasing open firmware for. Sorry, but we just don't see a commitment to an open ecosystem.

  3. Odgovor korisnicima i sljedećem broju korisnika:

    Meanwhile, RISC-V still doesn't have a proper vector extension, and fragmentation is a massive problem. Debian archives are only at ~50% coverage for RISC-V vs. 95%+ for OpenPOWER. Also, widest deployments are all crypto locked, very little incentive to develop for it.👎

  4. prije 6 sati

    Our latest blog explores how SoCs based on can use an alternate approach to bypass the Last-Level Cache, avoiding the traditional difficulty of data transfers between a DSA and memory. For more:

  5. prije 8 sati

    I'm excited to be speaking about how 's framework is helping to scale the developer ecosystem.

  6. Thanks to for highlighting our predictions for 2020. 2019 was a great year for , looking forward to working with all our customers and partners in 2020 - embracing the flexibility of , processor optimizations with extensions, virtua…

  7. prije 11 sati

    Spreading the love with a Valentine's eve night SW tools focused meetup. Antmicro, OneSpin Solutions, Bluespec, Inc, IAR Systems and Ashling will present

  8. prije 17 sati

    Don't miss the Jan/Feb 2020 edition of magazine: with Touch (, ), AC Motor Drive, Extendable Enviro Monitoring Syst, Tracker, , Text for , and more!

  9. prije 23 sata

    Black Parrot talk at devroom at

  10. 2. velj

    RISC-V meetup in Munich 28 Feb! Check out RISC-V First Meetup at HM Munich with Florian Wohlrab

  11. 2. velj

    I hope you enjoy and that you get a chance to checkout the craze about

  12. 2. velj

    Check out this Meetup for RISC-V: Munich RISC-V First Meetup at Hochschule Munich    via

  13. 2. velj

    The seL4 is doing quite well on ! Starting the day at in the micro kernel devroom.

  14. 1. velj

    BlackParrot an open source based as an Intel Xeon "competitor".

  15. 31. sij

    Blog: "High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V" by

  16. 29. sij
    Prikaži ovu nit
  17. 28. sij

    Join us for our next RISC-V Bay Area Meetup - "Discover RISC-V SW tools you will love"! This event is free and will be held on February 13th at 5:30 in Milpitas...

  18. 28. sij

    Our collaboration with continues when we develop our new processors like the NOEL-V.

  19. 28. sij

    Our new SVP of Platform Engineering shares why he’s excited to join the SiFive team and what he hopes to accomplish. Check it out here:

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