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Joel Sing just finished landing the RISC-V port to the almost-out
#golang 1.14! It works!
(We'd made a special exception to let the #riscv stuff land during the freeze since it was mailed prior to the freeze, sufficiently isolated, and distros/people were waiting on it.) pic.twitter.com/slUMO5brgH
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More importantly, the only way to get an open firmware
#RISCV device is to either use a slow FPGA variant or buy a small, low power chip that the silicon vendor had to be embarrassed into releasing open firmware for. Sorry, but we just don't see a commitment to an open ecosystem. -
Meanwhile, RISC-V still doesn't have a proper vector extension, and fragmentation is a massive problem. Debian archives are only at ~50% coverage for RISC-V vs. 95%+ for OpenPOWER. Also, widest
#RISCV deployments are all crypto locked, very little incentive to develop for it.
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Our latest blog explores how SoCs based on
@risc_v can use an alternate approach to bypass the Last-Level Cache, avoiding the traditional difficulty of data transfers between a DSA and memory. For more: https://sifive.com/blog/high-bandwidth-accelerator-access-to-memory-enabling-optimized-data-transfers-with-risc-v …#riscv#ideatosilicon#datatransfers -
I'm excited to be speaking about how
@antmicro's#opensource#Renode framework is helping to scale the#RISCV developer ecosystem. https://twitter.com/teodoroj/status/1224379003106021376 … -
Thanks to
#EDACafe for highlighting our predictions for 2020. 2019 was a great year for#Imperas, looking forward to working with all our customers and partners in 2020 - embracing the flexibility of#RISCV, processor optimizations with extensions, virtua…https://lnkd.in/dTrMsS3 -
Spreading the
#riscv love with a Valentine's eve night SW tools focused meetup. Antmicro, OneSpin Solutions, Bluespec, Inc, IAR Systems and Ashling will present https://lnkd.in/gmD8fZB -
Don't miss the Jan/Feb 2020 edition of
#Elektor magazine:#GUI with Touch (#ESP32,#RPi), AC Motor Drive, Extendable Enviro Monitoring Syst,#DIY#LoRa Tracker,#RISCV, Text for#Microcontroller, and more! https://www.elektormagazine.com/magazine/elektor-139 …#electronics#maker#DIYelectronics#techpic.twitter.com/96OF2o23LP
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Black Parrot talk at
#riscv devroom at#FOSDEMpic.twitter.com/soVg2gn34y
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RISC-V meetup in Munich 28 Feb! Check out RISC-V First Meetup at HM Munich
@risc_v with@Andes_Tech Florian Wohlrab https://www.meetup.com/Munich-RISC-V-Meetup-Group/events/268318683/ …#riscv#startups#ISA#Meetup#München#Munich -
@GeekDad412 I hope you enjoy#FOSDEM2020 and that you get a chance to checkout the craze about#RISCV -
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The seL4 is doing quite well on
#riscv! Starting the day at#FOSDEM2020 in the micro kernel devroom.pic.twitter.com/iixu4eXv7U
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BlackParrot an open source
#RiscV based#SoC as an Intel Xeon "competitor".#FOSDEM2020#isa#oshw#fpgapic.twitter.com/qFYhR0Y435
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Blog: "High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V" by
@sifive https://www.design-reuse.com/industryexpertblogs/47462/enabling-optimized-data-transfers-with-risc-v.html …#semIP#riscv -
Report: “RISC-V Genealogy” (Tony Chen & David Patterson, 2016)
https://content.riscv.org/wp-content/uploads/2016/02/EECS-2016-6.pdf …
Poster: “RISC-V Instruction Set Lineage”
https://content.riscv.org/wp-content/uploads/2016/02/RISC-V-Instruction-Lineage-Poster-v6.pdf …
#RISCV#ComputingHistorypic.twitter.com/px1Gkcnrfh
Prikaži ovu nit -
Join us for our next RISC-V Bay Area Meetup - "Discover RISC-V SW tools you will love"! This event is free and will be held on February 13th at 5:30 in Milpitas...
#riscv https://www.meetup.com/Bay-Area-RISC-V-Meetup/events/268276241/ … -
Our collaboration with
@AldecInc continues when we develop our new processors like the NOEL-V.#riscv#processor#computinghttps://twitter.com/AldecInc/status/1222214049057906689 …
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Our new SVP of Platform Engineering
@clattner_llvm shares why he’s excited to join the SiFive team and what he hopes to accomplish. Check it out here: https://www.sifive.com/blog/with-sifive-we-can-change-the-world …#ideatosilicon#riscv
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