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Even *more* talks announced just now for
#ORConf 2018
Check the entire list out here: https://orconf.org/#presentations
#prjxray#reverseengineering#cocotb#riscv#FOSSi@FossiFoundation -
Cocotb is a testbench environment for verifying RTL code using Python, and it could change the way you build FPGAs. Here's how you can use it to update the generic values that allow static parameters to apply to your entire design unit. https://buff.ly/2EoZQga
#FPGA#cocotb pic.twitter.com/JoVWAuQvj0
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Talking about the new features of Teros HDL
#ORConf#Vunit#cocotb#edalize#eda#vhdl#verilog#verilatorpic.twitter.com/x5ov2iKprp
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Hey! Look what came through by mail
and will commute with me from now on
@FossiFoundation &#cocotb swag! Thanks@wallento
pic.twitter.com/AHwoF7KuDE
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LibreCores CI base image already includes
#Cocotb and allows running it, but it would be great to add auxiliary tools like imphil/cocotb-testrunner. https://github.com/librecores/docker-images/tree/master/librecores-ci …Prikaži ovu nit -
You're at FOSDEM and want to know what's going on at
@lowRISC, at the@FossiFoundation, in#cocotb, at@librecores, or in any of the other projects I seem to be involved in? Ping me and let's talk! -
Thanks for a great 8th Wroclaw Open Source Meetup! Happy to see the growing interest in open tools such as our suite for testing
#USB IP cores w/#Cocotb &#Python, and adding practical integrations like#Wireshark and@gnutools#GDB to@renodeio /@CHIPSAlliance@linuxfoundationpic.twitter.com/ZVgHh7SnCy
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If you are designing your gateware with
#chisel Chisel and testing it with#cocotb, you will need some script (in#python) like that.https://github.com/Martoni/chisverilogutils … -
Want to implement
#USB support in your#FPGA design? See Antmicro's#opensource test suite for#USB IP cores based on#Python and#Cocotb at@CHIPSAlliance booth no. 123 at the#RISCVSummit and find out how we can be of help: https://antmicro.com/blog/2019/12/testing-usb-cores-with-python-and-cocotb/ …@RISC_Vpic.twitter.com/LxsJo9FcAK
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Come see the
#chisel and#cocotb demos in our booth at the#riscvsummit on Dec 10 & 11. We are in booth location #123. Just for stopping by, we'll give you this great screen/glasses cleaner! Register for a free expo pass. https://registration.n200.com/survey/0abpymh1nyg9f …?pic.twitter.com/hpDnhm30qU
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Our new
#opensource suite for testing#USB IP cores in#Python with#Cocotb provides a developer-friendly, unified framework for apples-to-apples behavior comparisons. Read more: https://antmicro.com/blog/2019/12/testing-usb-cores-with-python-and-cocotb/ …@CHIPSAlliance@risc_vpic.twitter.com/hrVQbzGGbs
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Presenting "HDL workflow in python" at
#SiFiveTechSymposium#bsas. i talked about#nmigen and#cocotb workflow and how it improves our development process. Presentation and material here https://github.com/andresdemski/sifive-bsas-hdl-python … -
Productive weekend at the
@CHIPSAlliance Open Source Design Verification Workshop in Munich. Antmicro presented on "Testing USB IP cores with a#Cocotb based#opensource test suite", followed by "Open source#SystemVerilog compliance test suite overview".@linuxfoundationhttps://twitter.com/OlofKindgren/status/1195268646639157248 …
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I would really like to get the TinyProg core tested using the new
@antmicro USB compliance suite written in#cocotb found at https://github.com/antmicro/usb-test-suite-build … It is currently being used to test the new Migen based ValentyUSB stack and another Verilog USB core. -
#orconf2019#cocotb is alive and kicking!! Thanks@MrImphil@wallento and@FossiFoundation for the amazing work.pic.twitter.com/lAHFJhBU2l
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FPGA development can be complicated, even for seasoned professionals, but cocotb can make it easier. Here's how it will help you verify your RTL code in Python, and how you can install it on Windows 10.
#FPGA#cocotb#FOSS https://buff.ly/2XkbeFk pic.twitter.com/3K6n8Wi9Qi
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Join
@antmicro discussing “Open Source Tools:#cocotb and#Verilator support” during the inaugural@CHIPSAlliance Workshop next week at Google’s Sunnyvale campus with@EsperantoTech,@Google,@SiFive &@WesternDigital@linuxfoundation: https://events.linuxfoundation.org/events/chips-alliance-workshop-2019/program/schedule/ …pic.twitter.com/ECgRWx9b2h
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I will present at the
@SiFive symposium in Munich today and talk about@FossiFoundation, my use of@risc_v in teaching and about#cocotb. Meet you there! -
Generic VHDL values allow static parameters like timing and size data to be sent from one architecture in a design unit, but apply to the whole of the design. Here's how to update those values in
#cocotb. https://buff.ly/2wjvnfi pic.twitter.com/NjbcJNmBED
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SystemVerilog and UVM present several big challenges to FPGA developers. They are large and complex, and require specialized knowledge.
#cocotb can help you overcome those challenges, and here's how to install it on Windows 10. https://buff.ly/2PA9XDx pic.twitter.com/l8ztUrSy5K
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