Rezultati pretraživanja
  1. 1. kol 2018.

    Even *more* talks announced just now for 2018 🤘 Check the entire list out here:

  2. 16. pro 2019.

    Cocotb is a testbench environment for verifying RTL code using Python, and it could change the way you build FPGAs. Here's how you can use it to update the generic values that allow static parameters to apply to your entire design unit.

  3. 28. ruj 2019.
  4. 7. lis 2019.

    Hey! Look what came through by mail ✉️ and will commute with me from now on 😍 & swag! Thanks ❤️

  5. 28. ruj 2019.

    LibreCores CI base image already includes and allows running it, but it would be great to add auxiliary tools like imphil/cocotb-testrunner.

    Prikaži ovu nit
  6. 31. sij

    You're at FOSDEM and want to know what's going on at , at the , in , at , or in any of the other projects I seem to be involved in? Ping me and let's talk!

  7. 30. sij

    Thanks for a great 8th Wroclaw Open Source Meetup! Happy to see the growing interest in open tools such as our suite for testing IP cores w/ & , and adding practical integrations like and to /

  8. 30. sij

    If you are designing your gateware with Chisel and testing it with , you will need some script (in ) like that.

  9. 11. pro 2019.

    Want to implement support in your design? See Antmicro's test suite for IP cores based on and at booth no. 123 at the and find out how we can be of help:

  10. 4. pro 2019.

    Come see the and demos in our booth at the on Dec 10 & 11. We are in booth location #123. Just for stopping by, we'll give you this great screen/glasses cleaner! Register for a free expo pass. ?

  11. 4. pro 2019.

    Our new suite for testing IP cores in with provides a developer-friendly, unified framework for apples-to-apples behavior comparisons. Read more:

  12. 22. stu 2019.

    Presenting "HDL workflow in python" at . i talked about and workflow and how it improves our development process. Presentation and material here

  13. 18. stu 2019.

    Productive weekend at the Open Source Design Verification Workshop in Munich. Antmicro presented on "Testing USB IP cores with a based test suite", followed by "Open source compliance test suite overview".

  14. 16. lis 2019.
    Odgovor korisnicima i sljedećem broju korisnika:

    I would really like to get the TinyProg core tested using the new USB compliance suite written in found at It is currently being used to test the new Migen based ValentyUSB stack and another Verilog USB core.

  15. 28. ruj 2019.

    is alive and kicking!! Thanks and for the amazing work.

  16. 19. lip 2019.

    FPGA development can be complicated, even for seasoned professionals, but cocotb can make it easier. Here's how it will help you verify your RTL code in Python, and how you can install it on Windows 10.

  17. 14. lip 2019.
  18. 22. svi 2019.

    I will present at the symposium in Munich today and talk about , my use of in teaching and about . Meet you there!

  19. 1. lis 2018.

    Generic VHDL values allow static parameters like timing and size data to be sent from one architecture in a design unit, but apply to the whole of the design. Here's how to update those values in .

  20. 28. ruj 2018.

    SystemVerilog and UVM present several big challenges to FPGA developers. They are large and complex, and require specialized knowledge. can help you overcome those challenges, and here's how to install it on Windows 10.

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