#ia64 #Itanium failed spectacularly. But probably poor #performance and bad #design were not the primary causes.
https://en.m.wikipedia.org/wiki/IA-64
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Itaniums failure is interesting, AFAICT the factors contributing to it were: Mistaken belief in the "sufficiently smart compiler" and the steepening of what is now the "memory wall"; binary incompatibility was then coupled with less-than-stellar performance.
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I've always thought this was a good source of lock-in for the incumbent, when competitors are designing for the same ISA (e.g., Intel and AMD). The incumbent still has to produce a chip that does OK on existing binaries, but they have some flexibility to introduce ...
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changes that require compiler changes, different optimization techniques, different behavior across any part of the uarch. Compilers and existing binaries will follow, because they are the incumbent, after all!
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The Stanford and Berkeley RISC projects of the early 80s, and their commercial offspring of the mid 80s (MIPS, SPARC, and others) were expressly and explicitly optimised in ISA and architecture to be able to *efficiently* implement the C virtual machine. ARM likewise via others.
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Yes, this is how CPU design has been mostly taught during least 3 decades, thanks to "Computer Architecture: A Quantitative Approach" (Patterson and Hennessy, 1989) My class had that textbook in 1999 and in here I am in 2020 doing pretty much what it says with my RISC-V core..
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One example of failed change is byte loads vs word. The first Alpha did not have byte loads but C makes it hard (64 bit byte being unpopular), and they thought that would be ok see https://web.cecs.pdx.edu/~herb/ece586w17/Papers/05_sites_alpha_1992.pdf …
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The came Windows NT/alpha and the EV56…
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*so many* machine architecture choices are made around how C works
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Čini se da učitavanje traje već neko vrijeme.
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