David Shah 

@fpga_dave

Open Source Electronics, FPGA and Software developer. Currently building open source tools for the ECP5 and other FPGAs. he/him or they/them

New Forest, UK
ds0.me
Vrijeme pridruživanja: studeni 2017.
129 fotografija ili videozapisa Fotografije i videozapisi

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  1. Prikvačeni tweet
    28. ruj 2019.

    My Patreon is now live! Will fund my work on supporting and developing nextpnr going forwards!

    26 replies 102 proslijeđena tweeta 243 korisnika označavaju da im se sviđa
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  2. proslijedio/la je Tweet
    28. pro 2019.

    if you've never played with FPGAs before and would like to give it a try, i highly recommend grabbing a seat and joining it! had tons of fun playing around with verilog for the first time and getting the iCEBreaker to do things and stuff!!!

    Getting ready for the second iCEBreaker FPGA workshop at in the Hardware Hacking area!
    5 proslijeđenih tweetova 25 korisnika označava da im se sviđa
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  3. 27. pro 2019.

    nextpnr now has a new json11 based frontend structured so new formats like flatbuffers will be easy to add in the future. Hierarchical netlists (Yosys -noflatten) are also supported. As ever, keep the bug reports flowing!

    9 proslijeđenih tweetova 65 korisnika označava da im se sviđa
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  4. 10. pro 2019.

    As Lattice launch their new parts, starting with a 40k CrossLink successor, I announce

    8 replies 39 proslijeđenih tweetova 152 korisnika označavaju da im se sviđa
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  5. proslijedio/la je Tweet
    5. pro 2019.

    Join the Lattice launch event webcast on December 10th 1:00 PM PST for the unveiling of our new products! Register now to watch keynotes from our management team and live demonstrations:

    2 proslijeđena tweeta 10 korisnika označava da im se sviđa
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  6. 22. stu 2019.

    PSA: If you are only using Yosys and SystemVerilog-capable tools, there's no reason to be using "always @*" for combinational logic and risking inferred latches - use "always_comb"

    5 proslijeđenih tweetova 51 korisnik označava da mu se sviđa
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  7. 18. stu 2019.

    The algorithm used is inspired by ; with some tweaks for the nextpnr Arch API, real-world special cases. Parallelism and SAT for very nasty congestion both WIP too...

    1 reply 21 korisnik označava da mu se sviđa
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  8. 18. stu 2019.

    Congestion heatmap (number of overused routing resources after 1 iteration of negotiated-congestion routing) for a LiteX SoC on ECP5 - note BRAM rows in middle and DDR3 IO at right edge. All part of nextpnr router2 development!

    1 reply 13 proslijeđenih tweetova 100 korisnika označava da im se sviđa
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  9. proslijedio/la je Tweet
    18. stu 2019.

    Project Apicula blinky!!! Super proud, and grateful for all the help I received.

    6 replies 16 proslijeđenih tweetova 90 korisnika označava da im se sviđa
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  10. proslijedio/la je Tweet
    10. stu 2019.

    I've released nMigen 0.1. onwards to simulator and standard library improvements in 0.2 now!

    21 proslijeđeni tweet 125 korisnika označava da im se sviđa
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  11. proslijedio/la je Tweet
    6. stu 2019.

    Here is my homebrew FPGA based PCI express video card up and running on Windows 10. The display only driver sample (which is the same code roughly as the basic display driver) is just that good to start from.

    155 proslijeđenih tweetova 1.004 korisnika označavaju da im se sviđa
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  12. 31. lis 2019.

    Lattice's new FDSOI FPGA platform supposedly ahead of schedule and to be announced/sampling in December. Excited to see what this brings and develop some tooling for it! (search FDSOI)

    1 reply 6 proslijeđenih tweetova 38 korisnika označava da im se sviđa
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  13. proslijedio/la je Tweet
    26. lis 2019.
    Odgovor korisniku/ci

    Finally you can subscribe on

    4 proslijeđena tweeta 24 korisnika označavaju da im se sviđa
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  14. 25. lis 2019.

    ❌Silicon Valley ✔️New Forest valleys

    1 proslijeđeni tweet 21 korisnik označava da mu se sviđa
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  15. proslijedio/la je Tweet
    24. lis 2019.

    Anyone know an open source (Verilog) simulator which supports SDF back annotation? Icarus seems to be missing a bunch of stuff, I can't see any support in Verilator and CVC isn't actually open source... Was sure I found something previously, but no luck finding anything now...

    1 reply 6 proslijeđenih tweetova 13 korisnika označava da im se sviđa
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  16. proslijedio/la je Tweet
    23. lis 2019.

    Now that the iCEBreaker FPGA campaign and pre-order fulfillment is completed. You can order iCEBreaker, Pmod and LED Panels in the regular store!

    1 reply 7 proslijeđenih tweetova 31 korisnik označava da mu se sviđa
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  17. 23. lis 2019.

    Added SDF back annotation to nextpnr; now post-place-and-route timing simulation is possible glitches et al! Unfortunately no open source sim seems to have good enough SDF support so having to use Xilinx xsim - demo here is picorv32 on iCE40HX

    5 replies 22 proslijeđena tweeta 112 korisnika označava da im se sviđa
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  18. proslijedio/la je Tweet
    14. lis 2019.

    I've released nMigen 0.1rc1! Feel free to try it for your projects; I think all the core parts are quite solid, and I don't anticipate any breaking HDL or stdlib changes, unless something truly broken is discovered.

    27 proslijeđenih tweetova 85 korisnika označava da im se sviđa
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  19. 13. lis 2019.

    Playing about with a simple SAT approach to FPGA-ish routing using ezSAT/minisat. Hopefully will find a home in nextpnr for cases where negotiated congestion gets stuck (not asking for optimal solution here, just any solution, also need to figure out how to deal with cycles)

    5 proslijeđenih tweetova 37 korisnika označava da im se sviđa
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  20. proslijedio/la je Tweet
    12. lis 2019.

    My talk about Open Source Formal Verification in VHDL is online!

    10 proslijeđenih tweetova 35 korisnika označava da im se sviđa
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  21. 12. lis 2019.

    The video of my ORConf 2019 talk on scaling up nextpnr is now online! Watch it here:

    9 proslijeđenih tweetova 47 korisnika označava da im se sviđa
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