eSilicon Corporation

@esiliconCorp

FinFET-class ASICs, market-specific IP platforms and 2.5D/HBM2 solutions for high-performance networking, computing, AI & 5G markets

Beigetreten April 2015

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  1. vor 23 Stunden

    Very big news for eSilicon today

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  2. 31. Okt.

    : Opposites Attract: IP Standardization vs. Customization — GSA Forum Optimizing PPA + minimizing cost and risk by fine-tuning key IP.

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  3. 30. Okt.

    “Best Partner in 2.5D ASIC Assembly” award: Thanks to ASE Kaohsiung for your incredible support on a very complex ASIC.

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  4. 30. Okt.

    eSilicon’s Ajay Lalwani presents the ASE Kaohsiung team with the “Best Partner in 2.5D ASIC Assembly” award. Thanks to ASE Kaohsiung for your incredible support on a very complex ASIC.

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  5. 22. Okt.

    Cohesity Case Study: eSilicon was managing billions of files, doing complete , something no other company has done before. enabled eSilicon to complete our move to for optimized customer solutions.

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  6. 17. Okt.

    Is Copper Dead? - The Samtec Blog Illuminating post on copper vs. ; eSilicon over 7-meter (23-foot) Samtec copper cable (2.2 Terabits per second) at

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  7. 17. Okt.

    eSilicon White Paper on Chiplets – Good Read - Semiwiki One of the benefits of using a chiplet approach is that you can develop each chiplet in a different technology node, and of course they can be from different manufacturers.

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  8. 7. Okt.

    New Video from the : Counterintuitive Intelligence: Doing More to Cost Less, a TCO Story; presented by Carlos Macian, eSilicon

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  9. 7. Okt.

    Blog Review: Oct. 2 eSilicon’s Mike Gianfagna files dispatches from the and : Long & Longer Reach

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  10. 7. Okt.

    ML, Edge Drive IP To Outperform Broader Chip Market

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  11. 3. Okt.

    Semiconductor leader eSilicon shifts to public cloud to gain business agility and IT efficiency powered by a business-driven -WAN edge platform

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  12. 2. Okt.

    Silver Peak Surpasses 1,500 Production Customer Milestone for the Business-Driven Unity EdgeConnect -WAN Edge Platform

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  13. hat retweetet
    22. Sept.

    eSilicon announced the availability of its 7nm High-Bandwidth Interconnect (HBI+) PHY for chiplets architectures. This their alternative to Intel MDIO and TSMC LIPINCON designed for CoWoS and EMIB. It runs @ 4 GT/s & is compliant with Intel's AIB 1.1 I/F.

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  14. 27. Sept.

    Week In Review: Design, Low Power: eSilicon debuts 7nm high-bandwidth interconnect (HBI)+ PHY IP. Hard IP block offers a high-bandwidth, low-power, low-latency PHY interface for 2.5D applications such as .

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  15. hat retweetet
    27. Sept.
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  16. 27. Sept.

    Long And Longer Reach SerDes – On The Road Again

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  17. 27. Sept.

    AI Hardware Summit, Report #1: Doing More to Cost Less - Semiwiki

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  18. 27. Sept.

    Opposites Attract: IP Standardization vs. Customization

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  19. 27. Sept.

    HPC Eases Its Way Into The Cloud

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  20. hat retweetet
    26. Sept.
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