Eric LaForest

I'm adding modules as I write them up (I have a few dozen ready to polish up). Here's a semi-silly example: a constant value module. http://fpgacpu.ca/fpga/Constant.html …

Here's a slightly less silly example, which has both beginner and expert uses: http://fpgacpu.ca/fpga/Bit_Reducer.html … (I'm also addressing Pull Requests and comments. Thanks!)

Here is a simple, generic binary Multiplexer, which cleanly replaces all those nested if-statements and ternary operators (please don't do that!), and simulates better too. #FPGA http://fpgacpu.ca/fpga/Multiplexer.html …

A Binary Up/Down Counter, built from Adder/Subtractor and Register modules, which each deal with a different difficulty in design (carry logic, and resets, respectively). Parameterized increment. Can be chained. Sets the form for future counters. http://fpgacpu.ca/fpga/Counter_Binary.html …

Another simple design element: the Annuller. Seems trivial, but it cleans up schematics, clarifies intent, guides thinking for parallelism, and is a building block for other important elements. http://fpgacpu.ca/fpga/Annuller.html …

And the Word Reducer. Word reduction doesn't exist in Verilog, so we have to create it. Two implementations. Also useful for parallelism and result-checking. http://fpgacpu.ca/fpga/Word_Reducer.html … #FPGA

A Word Reverser: depending on how you set it, can do full bit-reversal, or byte-endianness reversal, or otherwise. No logic cost: it just moves wires around. http://fpgacpu.ca/fpga/Word_Reverser.html … #FPGA

A Bit Voting module: tells you if you have a minority/majority/tie/unanimity of set bits in a word. Useful for checking for divergences in operation. http://fpgacpu.ca/fpga/Bit_Voting.html …

The clog2 function, which isn't built-in until Verilog-2005 and SystemVerilog. Allows an enclosing module to only know the number of items to have counted, pass it as a parameter, and the sub-module determines the bit width for a counter or other index. http://fpgacpu.ca/fpga/clog2_function.html …

A generalized bit-shifter building block. Logic only. Wire it up as needed to implement the particular shift/rotate you need, which also incidentally specializes the logic to something smaller. http://fpgacpu.ca/fpga/Bit_Shifter.html … #FPGA

A binary demultiplexer, with a conservative design: unselected outputs are always zero. Cleans up simulations and safeguards from snooping. http://fpgacpu.ca/fpga/Demultiplexer_Binary.html … #FPGA

On second thought, sometimes you may want to broadcast when demultiplexing, so I added that as an implementation option. http://fpgacpu.ca/fpga/Demultiplexer_Binary.html …

Which also led me to update the section on assign statements in my Verilog Coding Standard to mention a synthesis pitfall when inferring tri-state I/O. http://fpgacpu.ca/fpga/verilog.html#assign …

A simulation clock that avoids a sneaky initial race condition which might cause X propagation. H/T to @oe1cxw for the knowledge. #FPGA http://fpgacpu.ca/fpga/Simulation_Clock.html …

A Register Pipeline for shifting, delaying, serial/parallel conversion, and shift-add algorithms. http://fpgacpu.ca/fpga/Register_Pipeline.html … #FPGA

A synthesis input harness, for rapid build checking and Fmax estimation. There's a corresponding output harness. http://fpgacpu.ca/fpga/Synthesis_Harness_Input.html …

A pipeline skid buffer (updated). It's a fundamental building block for AXI, elastic pipelines, and any processing block that uses ready/valid handshakes. Think of it as an extension of the plain pipeline register. (the old link redirects to this one) http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html …

A static address translator. Converts an arbitrary N-location decoded address range into a 0 to N-1 index for addressing hardware like registers and multiplexers. Simple logic, but tricky to write without causing CAD warnings or poor synthesis. http://fpgacpu.ca/fpga/Address_Translator_Static.html …