Eric LaForest

@elaforest

GateForge Consulting Ltd. | FPGA design services & software | Xilinx | Intel | AWS F1

Toronto, Ontario
fpgacpu.ca/gateforge/inde…
Vrijeme pridruživanja: studeni 2009.
62 fotografije ili videozapisa Fotografije i videozapisi

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  1. Prikvačeni tweet
    29. lis 2019.

    I'm writing an online book: "FPGA Design Elements", which provides a reference library of fundamental digital logic design elements. Think of it as a hardware analog to the C Standard Library ("libc") and its documentation.

    9 replies 78 proslijeđenih tweetova 269 korisnika označava da im se sviđa
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  2. prije 16 sati

    This is impressive and fresh. I've been using these tools for 25 years, and I still learnt something new.

    0:45
    In January, , , and I ran a short class at on topics we think are missing in most CS programs — tools we use every day that everyone should know, like bash, git, vim, and tmux. And now the lecture notes and videos are online!
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  3. prije 21 sat

    This was driven by also compiling and installing Icarus Verilog: I had code that linted cleanly in Verilator, synthesized cleanly in Vivado 2018.3, but didn't simulate correctly in XSim, showing an impossible outcome. It simulated fine in iverilog.

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  4. prije 21 sat

    Took the trouble to build gtkwave 3.3.103 from source, rather than use the 3.3.66 (from 2015!) in Ubuntu 16.04 LTS. Very, very fast, and nicer to look at. Look at the notes in README for necessary dev packages and good config options.

    1 reply 2 proslijeđena tweeta 7 korisnika označava da im se sviđa
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  5. proslijedio/la je Tweet
    23. sij

    Doing floating point division without using floating point division. . Might be useful for and

    5 proslijeđenih tweetova 36 korisnika označava da im se sviđa
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  6. 17. sij

    Second-to-last Toronto FPGA Users Group online meetup, Jan 22, 8:30pm EST. No agenda. Everyone welcome. Just FPGA and computer design discussion. Come ask a question, show off your project, or just be curious. Discord invite:

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  7. 14. sij

    A dynamic (arithmetic) address translator. Same idea as the static translator above, but much simpler and the offset can be readjusted on-the-fly. Not guaranteed to optimize down to LUT logic when given constant inputs.

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  8. 10. sij

    A static address translator. Converts an arbitrary N-location decoded address range into a 0 to N-1 index for addressing hardware like registers and multiplexers. Simple logic, but tricky to write without causing CAD warnings or poor synthesis.

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  9. 7. sij

    This is a good thing. I've written a smidge of BlueSpec. While it has its problems, like any HDL, it can be quite powerful. And I know it's used in industry for some serious, mature work.

    2 proslijeđena tweeta 17 korisnika označava da im se sviđa
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  10. 29. pro 2019.

    A pipeline skid buffer (updated). It's a fundamental building block for AXI, elastic pipelines, and any processing block that uses ready/valid handshakes. Think of it as an extension of the plain pipeline register. (the old link redirects to this one)

    3 proslijeđena tweeta 16 korisnika označava da im se sviđa
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  11. 29. pro 2019.

    A synthesis input harness, for rapid build checking and Fmax estimation. There's a corresponding output harness.

    1 reply 1 proslijeđeni tweet 6 korisnika označava da im se sviđa
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  12. proslijedio/la je Tweet
    21. pro 2019.

    2020 is going to be a strange year for Reconfigurable computing conferences with 3/4 top venues located in the US — FPGA, FCCM, and FPT are all in the US. Only FPL is in Europe. This distribution is representative of neither the FPGA market nor its practitioners/users.

    3 proslijeđena tweeta 16 korisnika označava da im se sviđa
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  13. 20. pro 2019.

    Multithreading to absorb delays on FPGA soft-processors is a great way to get more work out of the same logic area.

    It is with great pleasure to announce the release of the open source Arduissimo project on github. Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programs on the ARTY board (XC7A35T).
    7 korisnika označava da im se sviđa
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  14. proslijedio/la je Tweet
    20. pro 2019.

    Looking at how ACM wants to keep papers behind paywalls with a US-centric justification of research, we must radically alter how we run the reconfigurable computing community.

    5 proslijeđenih tweetova 22 korisnika označavaju da im se sviđa
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  15. 9. pro 2019.

    A Register Pipeline for shifting, delaying, serial/parallel conversion, and shift-add algorithms.

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  16. 28. stu 2019.

    A simulation clock that avoids a sneaky initial race condition which might cause X propagation. H/T to for the knowledge.

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  17. 27. stu 2019.

    Which also led me to update the section on assign statements in my Verilog Coding Standard to mention a synthesis pitfall when inferring tri-state I/O.

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  18. 27. stu 2019.

    On second thought, sometimes you may want to broadcast when demultiplexing, so I added that as an implementation option.

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  19. 26. stu 2019.

    A binary demultiplexer, with a conservative design: unselected outputs are always zero. Cleans up simulations and safeguards from snooping.

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  20. 26. stu 2019.

    A generalized bit-shifter building block. Logic only. Wire it up as needed to implement the particular shift/rotate you need, which also incidentally specializes the logic to something smaller.

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  21. 22. stu 2019.

    Toronto FPGA Users Group Discord chat is next Wed, Nov 27, 8:30pm EST. No agenda. Everyone welcome. Drop-in anytime! Just FPGA and computer design discussion. Come ask a question, show off your project, or just be curious.

    1 proslijeđeni tweet 2 korisnika označavaju da im se sviđa
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