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  1. proslijedio/la je Tweet

    In related news, my yosys+nextpnr+prjleuctra flow has just finally spit out a working picorv32 bitstream for Spartan 6.

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  2. 27. sij

    Go fat yourself.

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  3. 19. sij

    The interesting reading for the weekend: Jim Hogan's Formal Guide and its insufficiencies: and with

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  4. 16. sij

    I don't trust anybody who says Model Checking/Static Functional Verification is easy, if he/she haven't read at least one of these books before. Either he/she doesn't fully understand it really, or just wants to sell something.

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  5. 12. sij
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  6. 9. sij

    Ring Oscillators (RO) Physical Unclonable Function (PUF) in Cyclone IV FPGA:

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  7. 3. sij
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  8. 3. sij

    The patent from Averant Static Coverage technology: ... dunno what happened with them, website looks outated.

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  9. 2. sij

    A *bunch* of papers, conferences, slides, etc, about FPGA:

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  10. 29. pro 2019.

    The other day I saw a tweet saying that, hard working minorities are underperformers. Around 2010's I was so poor I can't even afford a pack of cookies for lunch; today, I'm not Bill Gates but I have all types of expensive FPGA kits thanks to hard work. Fuck off, efforts pay off

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  11. 22. pro 2019.

    I was about to teach him some fpga stuff, but turns out he needs to learn first how to not poop his own bed. I guess that's more important right now.

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  12. proslijedio/la je Tweet
    10. pro 2019.

    join and in our next webinar: … They will be discussing Dan's experience & use of Formal to verify bus transaction.

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  13. proslijedio/la je Tweet

    As Lattice launch their new parts, starting with a 40k CrossLink successor, I announce

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  14. 9. pro 2019.

    This weekend I tried to work on OpenVINO with my Arria 10 board. The Intel installer is really a headache. I wasn't able to do much. I think they like to complicate things so you work on their cloud instead. That's very bad practice.

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  15. 9. pro 2019.

    *My way of coding is so industry standard (dirty, quick, ugly, but werks), that I might get a job at Cadence with no issues.* Next week after that thought... Well, 4 years of not doing sw at all, I'm not that stupid I think. Yet I want to improve a lot of things.

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  16. 4. pro 2019.

    tusSAT, and FPGA (VHDL) based SAT solver (DPLL algorithm).

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  17. proslijedio/la je Tweet
    29. stu 2019.

    My latest Hackster project is an in-depth Vitis embedded flow example creating a simple MiniZed Motor Control application. '

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  18. proslijedio/la je Tweet
    27. stu 2019.

    This week, I am showing how to create a Linux Virtual Machine for Vitis when using the acceleration flow

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  19. 24. stu 2019.

    Got the ARM MPS2+ to do a bring-up of the M3+mbed subsystem. That Cyclone V is not a SoC.

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  20. proslijedio/la je Tweet
    18. stu 2019.
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