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Diego H proslijedio/la je Tweet
In related news, my yosys+nextpnr+prjleuctra flow has just finally spit out a working picorv32 bitstream for Spartan 6.
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Go fat yourself.
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The interesting reading for the weekend: Jim Hogan's Formal Guide and its insufficiencies: http://www.deepchip.com/items/0558-04.html … and https://www.deepchip.com/items/0558-06.html … with http://www.deepchip.com/items/0562-06.html …
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I don't trust anybody who says Model Checking/Static Functional Verification is easy, if he/she haven't read at least one of these books before. Either he/she doesn't fully understand it really, or just wants to sell something.pic.twitter.com/PVc97TC193
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Terasic T-core (MAX10) is shipping a SiFive E300 RISC-V demo: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=1230&PartNo=1 …
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Ring Oscillators (RO) Physical Unclonable Function (PUF) in Cyclone IV FPGA: http://www2.informatik.uni-freiburg.de/~feiten/publications/feiten_2018_trudevice18.pdf …pic.twitter.com/p79MQvv9Dh
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They have a YouTube channelhttps://www.youtube.com/channel/UCxNY-hxzJFa6zNSv94Vp1-Q …
Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
The patent from Averant Static Coverage technology: https://patentimages.storage.googleapis.com/44/63/59/9d5801b79f146c/US6594804.pdf … ... dunno what happened with them, website looks outated.
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A *bunch* of papers, conferences, slides, etc, about FPGA: http://hartenstein.de/FPGA_papers/
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The other day I saw a tweet saying that, hard working minorities are underperformers. Around 2010's I was so poor I can't even afford a pack of cookies for lunch; today, I'm not Bill Gates but I have all types of expensive FPGA kits thanks to hard work. Fuck off, efforts pay off
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I was about to teach him some fpga stuff, but turns out he needs to learn first how to not poop his own bed. I guess that's more important right now.pic.twitter.com/RC8KGWU0hx
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Diego H proslijedio/la je Tweet
join
@zipcpu and@matthewvenn in our next webinar: http://bit.ly/2P8ox6J … They will be discussing Dan's experience & use of Formal to verify bus transaction.Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Diego H proslijedio/la je Tweet
As Lattice launch their new parts, starting with a 40k CrossLink successor, I announcehttps://github.com/daveshah1/prjoxide …
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This weekend I tried to work on OpenVINO with my Arria 10 board. The Intel installer is really a headache. I wasn't able to do much. I think they like to complicate things so you work on their cloud instead. That's very bad practice.pic.twitter.com/73GMqbIJ1y
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*My way of coding is so industry standard (dirty, quick, ugly, but werks), that I might get a job at Cadence with no issues.* Next week after that thought... Well, 4 years of not doing sw at all, I'm not that stupid I think. Yet I want to improve a lot of things.pic.twitter.com/MXhGNQfFCc
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tusSAT, and FPGA (VHDL) based SAT solver (DPLL algorithm).https://github.com/Sumith1896/tusSAT …
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Diego H proslijedio/la je Tweet
My latest Hackster project is an in-depth Vitis embedded flow example creating a simple MiniZed Motor Control application. '
#fpga#arm#softwareengineeering#enginering#software#xilinx#electronics#programming#engineershttps://lnkd.in/gPGR3tbHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Diego H proslijedio/la je Tweet
This week, I am showing how to create a Linux Virtual Machine for Vitis when using the acceleration flow
#fpga#softwareengineering#software#acceleration#arm#pynq#softwareengineeering#xilinx#embeddedsystems#electronicshttps://lnkd.in/gNduncxHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Got the ARM MPS2+ to do a bring-up of the M3+mbed subsystem. That Cyclone V is not a SoC.pic.twitter.com/SanmIT4hT1
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Diego H proslijedio/la je TweetHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
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