@kellabyte And, in multi-processor cache coherency, "fence" is used as similar explicit signal for synchronization.
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Replying to @pbailis
@kellabyte More on this here: http://en.wikipedia.org/wiki/Memory_barrier …; cache coherency is just about as confusing as distributed consistency!2 replies 2 retweets 2 likes -
Replying to @pbailis
@pbailis@kellabyte Modern multicores are distributed systems except partial failure will likely panic your OS not 'completed maybe' on you!2 replies 0 retweets 0 likes -
Replying to @darachennis
@darachennis@pbailis We're just repeating what telecoms already built. They already handled partial failures at the hardware/OS level.1 reply 0 retweets 1 like -
Replying to @kellabyte
@kellabyte@pbailis Erlang/OTP and Dr Bits work on Platform Agnostic Bit Technology (cc@Omerk - Actor model for hardware madness)2 replies 0 retweets 0 likes -
Replying to @darachennis
@darachennis@pbailis@Omerk In high school summer job at Nortel the lang + framework was actor based & you could yank motherboard out live1 reply 0 retweets 1 like -
Replying to @kellabyte
@kellabyte@pbailis@OmerK That basically "Carrier grade"1 reply 0 retweets 0 likes -
Replying to @darachennis
@darachennis@pbailis@OmerK Ya. I think most of what we are doing in distsys today or multi-core already figured out 20 yrs ago in telecom3 replies 0 retweets 0 likes -
Replying to @kellabyte
@kellabyte@darachennis@OmerK Well, the overheads of communication are limited on a single system, but I agree there are serious parallels.1 reply 0 retweets 0 likes -
Replying to @pbailis
@pbailis@darachennis@OmerK It was all networked via fiber channels I believe. Partitions happened regardless if it was encased in a box :)1 reply 0 retweets 0 likes
@kellabyte @pbailis @OmerK Solace hardware designed so even if you take an axe to one, you can hot swap flash state to a secondary & recover
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