Periodic reminder that basically every "RISC is obsolete" / "RISC is unscalable" article is based on a faulty assumption. RISC has never been about not having instructions like FJCVTZS.pic.twitter.com/1ozoH5MWgL
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What is RISC? https://danluu.com/risc-definition/ … Hint: it's not about the number of instructions.pic.twitter.com/2YLL4tBWkS
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To be fair, RISC is probably one of the worst named concepts in computer science. John Mashey spent a decade correcting people on Usenet and couldn't stem the tide of people who naively thought that the concept was defined by the name.
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People say dynamic programming is a ridiculous name, and it is, but at least it's merely meaningless.pic.twitter.com/vqz7qRD74N
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Is there any index of these posts that aren't linked from the front page of http://danluu.com ?
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Not right now, unfortunately. They tend to be older, so you can get to them via the bottom left/right arrows, but that's pretty inconvenient
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our architects (GPU, but still) have told us that the cost of icache (silicon for it + fetch cost) justifies almost any decode complexity
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decode (including variable length) is just a few more wires: it's almost more of an overhead on the humans dealing with the ISA than RTL
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Any-length is definitely expensive, but 6-8 stages for fetch/decode is not really a fn of that - pretty typical even for "RISCier" designs.
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E.g. ARM Cortex-A72 has 8-stage fetch+decode; Cortex-A73 has 4 stages fetch+decode, and IIRC the Cell PPE had 8 (was it 9?) despite
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well, yeah, the font size was small and the uop mappings weren't explained, just lists of inexplicable acronyms alongside opcodes
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also, same architects had daydreams of a world where they could eliminate 32-bit ARM because it'd vastly simplify the chip.......
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