Watch your #semieda language! Why hardware development is hard, part 1: Verilog is weird http://danluu.com/why-hardware-development-is-hard/ … via @danluu
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Replying to @grep1 reply 0 retweets 0 likes
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Replying to @Daniel_J_Payne
@Daniel_J_Payne@grep Yeah, the last time I touched VHDL was for https://github.com/danluu/sega-system-for-fpga/ …, in '02, and we ended up switching to Verilog.1 reply 0 retweets 0 likes
@Daniel_J_Payne @grep Wait, I did have to use it a year later at IBM. But, I've managed to avoid ti since then :-).
12:49 PM - 13 Nov 2013
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