Watch your #semieda language! Why hardware development is hard, part 1: Verilog is weird http://danluu.com/why-hardware-development-is-hard/ … via @danluu
@Daniel_J_Payne @grep Yeah, the last time I touched VHDL was for https://github.com/danluu/sega-system-for-fpga/ …, in '02, and we ended up switching to Verilog.
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@Daniel_J_Payne@grep Wait, I did have to use it a year later at IBM. But, I've managed to avoid ti since then :-).Thanks. Twitter will use this to make your timeline better. UndoUndo
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