If 1k out of 1k failed under load, the chip never would've shipped in the first place, you're never going to see that. The linked bug is contemporary with the NaCl thread. How come the CPU vendor *most likely to have issues like the one you describe* is one of two whitelisted?
No, and I never said that. The bug we ran into causes effectively arbitrary data corruption. I admit I haven't read all of the NaCl code, but I would be pretty surprised if it's robust against arbitrary data corruption.
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I think you don't understand the NaCl security model, could you at least read the paper before being so angry about it? We need obscure parts of the spec that were *never* security relevant before to work under adversarial conditions, like segmentation edge cases.
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If you don't handle reading a dword across a segment boundary the same way intel does, then remote code execution. How confident are you do? I didn't test, I bet I can find edge cases you deviate in. I'll bet money on this.
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I'd be curious to know how reading CPU errata is helpful. A typical errata will say something like "under certain conditions, unexpected behavior may occur" and it will then describe corruption of {cache, registers, IP, flags, etc.} What can any software do to work around that?
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There are tens to hundreds of errata like this for a modern Intel CPU. When you say that NaCl depends on a limited subset of features, are you saying this subset of features does not include having correct values in registers, memory, flags, etc.?
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